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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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H838532H датащи(PDF) 238 Page - Renesas Technology Corp |
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H838532H датащи(HTML) 238 Page - Renesas Technology Corp |
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238 / 508 page  Section 9 Timers Rev. 1.00 May 30, 2008 Page 218 of 484 REJ09B0436-0100 Bits 6 and 5: Counter up/down control (TMC6, TMC5) Selects whether TCC up/down control is performed by hardware using UD pin input, or whether TCC functions as an up-counter or a down-counter. Bit 6 TMC6 Bit 5 TMC5 Description 0 0 TCC is an up-counter (initial value) 0 1 TCC is a down-counter 1 * Hardware control by UD pin input UD pin input high: Down-counter UD pin input low: Up-counter *: Don’t care Bits 4 and 3: Reserved bits Bits 4 and 3 are reserved; they are always read as 1 and cannot be modified. Bits 2 to 0: Clock select (TMC2 to TMC0) Bits 2 to 0 select the clock input to TCC. For external event counting, either the rising or falling edge can be selected. Bit 2 TMC2 Bit 1 TMC1 Bit 0 TMC0 Description 0 0 0 Internal clock: φ/8192 (initial value) 0 0 1 Internal clock: φ/2048 0 1 0 Internal clock: φ/512 0 1 1 Internal clock: φ/64 1 0 0 Internal clock: φ/16 1 0 1 Internal clock: φ/4 1 1 0 Internal clock: φw/4 1 1 1 External event (TMIC): rising or falling edge* Note: * The edge of the external event signal is selected by bit IEG1 in the IRQ edge select register (IEGR). See (1) IRQ Edge Select Register (IEGR) in 3.3.2, Interrupt Control Registers, for details. IRQ1 must be set to 1 in port mode register 1 (PMR1) before setting 111 in bits TMC2 to TMC0. |
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