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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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H838532H датащи(PDF) 90 Page - Renesas Technology Corp |
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H838532H датащи(HTML) 90 Page - Renesas Technology Corp |
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90 / 508 page  Section 3 Exception Handling Rev. 1.00 May 30, 2008 Page 70 of 484 REJ09B0436-0100 Bit 6: A/D converter interrupt request flag (IRRAD) Bit 6 IRRAD Description 0 Clearing condition: (initial value) When IRRAD = 1, it is cleared by writing 0 1 Setting condition: When A/D conversion is completed and ADSF is cleared to 0 in ADSR Bit 5: Reserved bit Bit 5 is a readable/writable reserved bit. It is initialized to 0 by a reset. Bit 4: Timer G interrupt request flag (IRRTG) Bit 4 IRRTG Description 0 Clearing condition: (initial value) When IRRTG = 1, it is cleared by writing 0 1 Setting condition: When the TMIG pin is designated for TMIG input and the designated signal edge is input, or when TCG overflows while OVIE is set to 1 in TMG Bit 3: Timer FH interrupt request flag (IRRTFH) Bit 3 IRRTFH Description 0 Clearing condition: (initial value) When IRRTFH = 1, it is cleared by writing 0 1 Setting condition: When TCFH and OCRFH match in 8-bit timer mode, or when TCF (TCFL, TCFH) and OCRF (OCRFL, OCRFH) match in 16-bit timer mode |
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