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H838532H датащи(PDF) 76 Page - Renesas Technology Corp |
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H838532H датащи(HTML) 76 Page - Renesas Technology Corp |
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76 / 508 page ![]() Section 2 CPU Rev. 1.00 May 30, 2008 Page 56 of 484 REJ09B0436-0100 • BCLR instruction executed BCLR #0, @RAM0 The BCLR instructions executed for the PCR5 work area (RAM0). • After executing BCLR instruction MOV.B @RAM0, R0L MOV.B R0L, @PCR5 The work area (RAM0) value is written to PCR5. P57 P56 P55 P54 P53 P52 P51 P50 Input/output Input Input Output Output Output Output Output Output Pin state Low level High level Low level Low level Low level Low level Low level High level PCR5 0 0 1 1 1 1 1 0 PDR5 1 0 0 0 0 0 0 0 RAM0 0 0 1 1 1 1 1 0 Table 2.13 lists the pairs of registers that share identical addresses. Table 2.14 lists the registers that contain write-only bits. Table 2.13 Registers with Shared Addresses Register Name Abbr. Address Timer counter and timer load register C TCC/TLC H'FFB5 Port data register 1* PDR1 H'FFD4 Port data register 3* PDR3 H'FFD6 Port data register 4* PDR4 H'FFD7 Port data register 5* PDR5 H'FFD8 Port data register 6* PDR6 H'FFD9 Port data register 7* PDR7 H'FFDA Port data register 8* PDR8 H'FFDB Port data register A* PDRA H'FFDD Note: * Port data registers have the same addresses as input pins. |
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