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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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H838532H датащи(PDF) 231 Page - Renesas Technology Corp |
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H838532H датащи(HTML) 231 Page - Renesas Technology Corp |
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231 / 508 page  Section 9 Timers Rev. 1.00 May 30, 2008 Page 211 of 484 REJ09B0436-0100 Bits 3 to 0: Internal clock select (TMA3 to TMA0) Bits 3 to 0 select the clock input to TCA. The selection is made as follows. Description Bit 3 TMA3 Bit 2 TMA2 Bit 1 TMA1 Bit 0 TMA0 Prescaler and Divider Ratio or Overflow Period Function 0 PSS, φ/8192 (initial value) 0 1 PSS, φ/4096 0 PSS, φ/2048 0 1 1 PSS, φ/512 0 PSS, φ/256 0 1 PSS, φ/128 0 PSS, φ/32 0 1 1 1 PSS, φ/8 Interval timer 0 PSW, 1 s 0 1 PSW, 0.5 s 0 PSW, 0.25 s 0 1 1 PSW, 0.03125 s 0 0 1 0 1 1 1 1 PSW and TCA are reset Clock time base (when using 32.768 kHz) (2) Timer Counter A (TCA) Bit Initial value Read/Write 7 TCA7 0 R 6 TCA6 0 R 5 TCA5 0 R 4 TCA4 0 R 3 TCA3 0 R 0 TCA0 0 R 2 TCA2 0 R 1 TCA1 0 R TCA is an 8-bit read-only up-counter, which is incremented by internal clock input. The clock source for input to this counter is selected by bits TMA3 to TMA0 in timer mode register A (TMA). TCA values can be read by the CPU in active mode, but cannot be read in subactive mode. When TCA overflows, the IRRTA bit in interrupt request register 1 (IRR1) is set to 1. |
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