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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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H838532H датащи(PDF) 97 Page - Renesas Technology Corp |
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H838532H датащи(HTML) 97 Page - Renesas Technology Corp |
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97 / 508 page  Section 3 Exception Handling Rev. 1.00 May 30, 2008 Page 77 of 484 REJ09B0436-0100 PC and CCR saved to stack SP (R7) SP – 1 SP – 2 SP – 3 SP – 4 Stack area SP + 4 SP + 3 SP + 2 SP + 1 SP (R7) Even address Prior to start of interrupt exception handling After completion of interrupt exception handling Legend: PCH: PCL: CCR: SP: Upper 8 bits of program counter (PC) Lower 8 bits of program counter (PC) Condition code register Stack pointer Notes: CCR CCR PCH PCL 1. 2. * PC shows the address of the first instruction to be executed upon return from the interrupt handling routine. Register contents must always be saved and restored by word access, starting from an even-numbered address. Ignored on return. * Figure 3.4 Stack State after Completion of Interrupt Exception Handling Figure 3.5 shows a typical interrupt sequence. |
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