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H838532H датащи(PDF) 89 Page - Renesas Technology Corp

номер детали H838532H
подробное описание детали  16-Bit Single-Chip Microcomputer H8 Family / H8/300H Super Low Power Series
PDF  508 Pages
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производитель  RENESAS [Renesas Technology Corp]
домашняя страница  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H838532H датащи(HTML) 89 Page - Renesas Technology Corp

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Section 3 Exception Handling
Rev. 1.00 May 30, 2008 Page 69 of 484
REJ09B0436-0100
Bit 5: Reserved bit
Bit 5 is reserved; it is always read as 1 and cannot be modified.
Bits 4 to 0: IRQ
4 to IRQ0 interrupt request flags (IRRI4 to IRRI0)
Bit n
IRRIn
Description
0
Clearing condition:
(initial value)
When IRRIn = 1, it is cleared by writing 0
1
Setting condition:
When pin
IRQn is designated for interrupt input and the designated signal edge is
input
(n = 4 to 0)
(5) Interrupt Request Register 2 (IRR2)
Bit
Initial value
Read/Write
7
IRRDT
0
R/W
6
IRRAD
0
R/W
5
—
0
R/W
4
IRRTG
0
R/W
3
IRRTFH
0
R/W
0
IRREC
0
R/W
2
IRRTFL
0
R/W
1
IRRTC
0
R/W
**
*
*
*
*
*
Note: * Only a write of 0 for flag clearing is possible
IRR2 is an 8-bit read/write register, in which a corresponding flag is set to 1 when a direct
transfer, A/D converter, Timer G, Timer FH, Timer FC, or Timer C interrupt is requested. The
flags are not cleared automatically when an interrupt is accepted. It is necessary to write 0 to clear
each flag.
Bit 7: Direct transfer interrupt request flag (IRRDT)
Bit 7
IRRDT
Description
0
Clearing condition:
(initial value)
When IRRDT = 1, it is cleared by writing 0
1
Setting condition:
When a direct transfer is made by executing a SLEEP instruction while DTON = 1 in
SYSCR2



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