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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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H838532H датащи(PDF) 88 Page - Renesas Technology Corp |
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H838532H датащи(HTML) 88 Page - Renesas Technology Corp |
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88 / 508 page  Section 3 Exception Handling Rev. 1.00 May 30, 2008 Page 68 of 484 REJ09B0436-0100 Bit 0: Asynchronous event counter interrupt enable (IENEC) Bit 0 enables or disables asynchronous event counter interrupt requests. Bit 0 IENEC Description 0 Disables asynchronous event counter interrupt requests (initial value) 1 Enables asynchronous event counter interrupt requests For details of SCI3-1 and SCI3-2 interrupt control, see section 10.2.6, Serial Control Register 3 (SCR3). (4) Interrupt Request Register 1 (IRR1) Bit Initial value Read/Write 7 IRRTA 0 R/W 6 — 0 R/W 5 — 1 — 4 IRRI4 0 R/W 3 IRRI3 0 R/W 0 IRRI0 0 R/W 2 IRRI2 0 R/W 1 IRRI1 0 R/W ** * ** * * Note: * Only a write of 0 for flag clearing is possible IRR1 is an 8-bit read/write register, in which a corresponding flag is set to 1 when a timer A or IRQ 4 to IRQ0 interrupt is requested. The flags are not cleared automatically when an interrupt is accepted. It is necessary to write 0 to clear each flag. Bit 7: Timer A interrupt request flag (IRRTA) Bit 7 IRRTA Description 0 Clearing condition: (initial value) When IRRTA = 1, it is cleared by writing 0 1 Setting condition: When the timer A counter value overflows from H'FF to H'00 Bit 6: Reserved bit Bit 6 is a readable/writable reserved bit. It is initialized to 0 by a reset. |
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