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H838532H датащи(PDF) 232 Page - Renesas Technology Corp |
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H838532H датащи(HTML) 232 Page - Renesas Technology Corp |
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232 / 508 page ![]() Section 9 Timers Rev. 1.00 May 30, 2008 Page 212 of 484 REJ09B0436-0100 TCA is cleared by setting bits TMA3 and TMA2 of TMA to 11. Upon reset, TCA is initialized to H'00. (3) Clock Stop Register 1 (CKSTPR1) — TFCKSTP TCCKSTP TACKSTP S31CKSTP S32CKSTP ADCKSTP TGCKSTP 7 6 543210 1 1111111 R/W R/W R/W R/W R/W R/W R/W R/W Bit Initial value Read/Write CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral modules. Only the bit relating to timer A is described here. For details of the other bits, see the sections on the relevant modules. Bit 0: Timer A module standby mode control (TACKSTP) Bit 0 controls setting and clearing of module standby mode for timer A. TACKSTP Description 0 Timer A is set to module standby mode 1 Timer A module standby mode is cleared (initial value) (4) Subclock Output Select Register (CWOSR) —— — CWOS ———— 7 6 543210 1 1111110 R R R R/W RRR R Bit Initial value Read/Write CWOSR is an 8-bit read/write register that selects the clock to be output from the TMOW pin. CWOSR is initialized to H'FE by a reset. Bits 7 to 1: Reserved bits Bits 7 to 1 are reserved; they are always read as 1 and cannot be modified. |
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