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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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H838532H датащи(PDF) 79 Page - Renesas Technology Corp |
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H838532H датащи(HTML) 79 Page - Renesas Technology Corp |
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79 / 508 page  Section 3 Exception Handling Rev. 1.00 May 30, 2008 Page 59 of 484 REJ09B0436-0100 Section 3 Exception Handling 3.1 Overview Exception handling is performed in this LSI when a reset or interrupt occurs. Table 3.1 shows the priorities of these two types of exception handling. Table 3.1 Exception Handling Types and Priorities Priority Exception Source Time of Start of Exception Handling High Reset Exception handling starts as soon as the reset state is cleared Low Interrupt When an interrupt is requested, exception handling starts after execution of the present instruction or the exception handling in progress is completed 3.2 Reset 3.2.1 Overview A reset is the highest-priority exception. The internal state of the CPU and the registers of the on- chip peripheral modules are initialized. 3.2.2 Reset Sequence As soon as the RES pin goes low, all processing is stopped and the chip enters the reset state. To make sure the chip is reset properly, observe the following precautions. • At power on: Hold the RES pin low until the clock pulse generator output stabilizes. • Resetting during operation: Hold the RES pin low for at least 10 system clock cycles. Reset exception handling takes place as follows. • The CPU internal state and the registers of on-chip peripheral modules are initialized, with the I bit of the condition code register (CCR) set to 1. • The PC is loaded from the reset exception handling vector address (H'0000 to H'0001), after which the program starts executing from the address indicated in PC. |
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