SH7261 datasheet(29/1348 Pages) RENESAS

29 / 1348 page

Rev. 2.00 Sep. 07, 2007 Page xxix of xxxii

24.4.2 Port D Data Register (PDDR)............................................................................. 1055

24.4.3 Port D Port Registers H and L (PDPRH and PDPRL) ........................................ 1056

24.5

Port E ............................................................................................................................... 1057

24.5.1 Register Configuration........................................................................................ 1057

24.5.2 Port E Port Register (PEPR) ............................................................................... 1057

24.6

Port F ............................................................................................................................... 1058

24.6.1 Register Configuration........................................................................................ 1058

24.6.2 Port F Data Register (PFDR) .............................................................................. 1059

24.6.3 Port F Port Register (PFPR)................................................................................ 1060

Section 25 Pin Function Controller (PFC).......................................................1061

25.1

Register Descriptions ....................................................................................................... 1069

25.1.1 Port A I/O Registers H and L (PAIORH and PAIORL) ..................................... 1071

25.1.2 Port A Control Registers 1 to 8 (PACR1 to PACR8) ......................................... 1072

25.1.3 Port B I/O Registers H and L (PBIORH and PBIORL) ...................................... 1082

25.1.4 Port B Control Registers 1 to 8 (PBCR1 to PBCR8) .......................................... 1083

25.1.5 Port C I/O Registers H and L (PCIORH and PCIORL) ...................................... 1096

25.1.6 Port C Control Registers 1 to 7 (PCCR1 to PCCR7) .......................................... 1097

25.1.7 Port D I/O Register (PDIOR).............................................................................. 1107

25.1.8 Port D Control Registers 1 to 5 (PDCR1 to PDCR5) ......................................... 1108

25.1.9 Port E Control Registers 1 and 2 (PECR1 and PECR2) ..................................... 1115

25.1.10 Port F I/O Register (PFIOR) ............................................................................... 1118

25.1.11 Port F Control Registers 1 and 2 (PFCR1 and PFCR2) ...................................... 1119

25.2

Usage Note....................................................................................................................... 1122

Section 26 On-Chip RAM ...............................................................................1123

26.1

Features............................................................................................................................ 1123

26.2

Usage Notes ..................................................................................................................... 1124

26.2.1 Page Conflict ...................................................................................................... 1124

26.2.2 RAME and RAMWE Bits .................................................................................. 1124

Section 27 Power-Down Modes ......................................................................1125

27.1

Features............................................................................................................................ 1125

27.1.1 Power-Down Modes ........................................................................................... 1125

27.2

Register Descriptions ....................................................................................................... 1127

27.2.1 Standby Control Register (STBCR).................................................................... 1128

27.2.2 Standby Control Register 2 (STBCR2)............................................................... 1129

27.2.3 Standby Control Register 3 (STBCR3)............................................................... 1131

27.2.4 Standby Control Register 4 (STBCR4)............................................................... 1132

27.2.5 Standby Control Register 5 (STBCR5)............................................................... 1134

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