SH7261 datasheet(14/1348 Pages) RENESAS

14 / 1348 page

Rev. 2.00 Sep. 07, 2007 Page xiv of xxxii

9.4.4

CSn Mode Register (CSMODn) (n = 0 to 6) ........................................................ 218

9.4.5

CSn Wait Control Register 1 (CS1WCNTn) (n = 0 to 6) ..................................... 221

9.4.6

CSn Wait Control Register 2 (CS2WCNTn) (n = 0 to 6) ..................................... 223

9.4.7

SDRAM Refresh Control Register 0 (SDRFCNT0) ............................................. 226

9.4.8

SDRAM Refresh Control Register 1 (SDRFCNT1) ............................................. 227

9.4.9

SDRAM Initialization Register 0 (SDIR0)........................................................... 229

9.4.10 SDRAM Initialization Register 1 (SDIR1)........................................................... 231

9.4.11 SDRAM Power-Down Control Register (SDPWDCNT) ..................................... 232

9.4.12 SDRAM Deep-Power-Down Control Register (SDDPWDCNT) ........................ 233

9.4.13 SDRAMm Address Register (SDmADR) (m = 0, 1)............................................ 234

9.4.14 SDRAMm Timing Register (SDmTR) (m = 0, 1) ................................................ 235

9.4.15 SDRAMm Mode Register (SDmMOD) (m = 0, 1)............................................... 237

9.4.16 SDRAM Status Register (SDSTR) ....................................................................... 238

9.4.17 SDRAM Clock Stop Control Signal Setting Register (SDCKSCNT) .................. 240

9.4.18 AC Characteristics Switching Register (ACSWR) ............................................... 241

9.5

Operation ........................................................................................................................... 242

9.5.1

CSC Interface........................................................................................................ 242

9.5.2

SDRAM Interface ................................................................................................. 252

9.6

Usage Note......................................................................................................................... 288

9.6.1

Note on Power-on Reset Exception Handling and Deep Standby Mode

Cancellation .......................................................................................................... 288

9.6.2

Write Buffer.......................................................................................................... 288

9.6.3

Note on Transition to Software Standby Mode or Deep Standby Mode............... 289

Section 10 Bus Monitor..................................................................................... 291

10.1

Register Descriptions ......................................................................................................... 291

10.1.1 Bus Monitor Enable Register (SYCBEEN) .......................................................... 292

10.1.2 Bus Monitor Status Register 1 (SYCBESTS1)..................................................... 293

10.1.3 Bus Monitor Status Register 2 (SYCBESTS2)..................................................... 295

10.1.4 Bus Error Control Register (SYCBESW)............................................................. 298

10.2

Bus Monitor Function ........................................................................................................ 299

10.2.1 Operation when a Bus Error is Detected............................................................... 299

10.2.2 Illegal Address Access Detection Function .......................................................... 300

10.2.3 Bus Timeout Detection Function .......................................................................... 302

10.2.4 Combinations of Masters and Bus Errors ............................................................. 303

10.3

Usage Note......................................................................................................................... 304

10.3.1 Operation when the CPU is Not Notified of a Bus Error...................................... 304

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