SH7261 datasheet(12/1348 Pages) RENESAS

12 / 1348 page

Rev. 2.00 Sep. 07, 2007 Page xii of xxxii

6.3.7

PINT Interrupt Request Register (PIRR) .............................................................. 130

6.3.8

Bank Control Register (IBCR).............................................................................. 131

6.3.9

Bank Number Register (IBNR) ............................................................................ 132

6.3.10 DMA Transfer Request Enable Register 0 (DREQER0) ...................................... 133

6.3.11 DMA Transfer Request Enable Register 1 (DREQER1) ...................................... 134

6.3.12 DMA Transfer Request Enable Register 2 (DREQER2) ...................................... 135

6.3.13 DMA Transfer Request Enable Register 3 (DREQER3) ...................................... 136

6.4

Interrupt Sources................................................................................................................ 137

6.4.1

NMI Interrupt........................................................................................................ 137

6.4.2

User Break Interrupt ............................................................................................. 137

6.4.3

H-UDI Interrupt .................................................................................................... 137

6.4.4

IRQ Interrupts....................................................................................................... 138

6.4.5

PINT Interrupts..................................................................................................... 139

6.4.6

On-Chip Peripheral Module Interrupts ................................................................. 139

6.5

Interrupt Exception Handling Vector Table and Priority................................................... 140

6.6

Operation ........................................................................................................................... 150

6.6.1

Interrupt Operation Sequence ............................................................................... 150

6.6.2

Stack after Interrupt Exception Handling ............................................................. 152

6.7

Interrupt Response Time.................................................................................................... 153

6.8

Register Banks ................................................................................................................... 158

6.8.1

6.8.2

Bank Save and Restore Operations....................................................................... 159

6.8.3

Save and Restore Operations after Saving to All Banks....................................... 161

6.8.4

6.8.5

6.9

Data Transfer with Interrupt Request Signals .................................................................... 163

6.9.1

Handling Interrupt Request Signals as Sources for CPU Interrupt but

not DMAC Activation .......................................................................................... 163

6.9.2

Handling Interrupt Request Signals as Sources for DMAC Activation but

not CPU Interrupt ................................................................................................. 163

6.10

Usage Note......................................................................................................................... 164

6.10.1 Timing to Clear an Interrupt Source ..................................................................... 164

Section 7 User Break Controller (UBC)............................................................ 165

7.1

Features.............................................................................................................................. 165

7.2

Input/Output Pin ................................................................................................................167

7.3

Register Descriptions ......................................................................................................... 167

7.3.1

Break Address Register (BAR)............................................................................. 168

7.3.2

Break Address Mask Register (BAMR) ............................................................... 169

7.3.3

Break Data Register (BDR) .................................................................................. 170

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