поискавой системы для электроныых деталей
  Russian  ▼
ALLDATASHEETRU.COM

X  

SH7261 датащи(PDF) 79 Page - Renesas Technology Corp

номер детали SH7261
подробное описание детали  32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
PDF  1348 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
производитель  RENESAS [Renesas Technology Corp]
домашняя страница  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7261 датащи(HTML) 79 Page - Renesas Technology Corp

Back Button SH7261 Datasheet HTML 75Page - Renesas Technology Corp SH7261 Datasheet HTML 76Page - Renesas Technology Corp SH7261 Datasheet HTML 77Page - Renesas Technology Corp SH7261 Datasheet HTML 78Page - Renesas Technology Corp SH7261 Datasheet HTML 79Page - Renesas Technology Corp SH7261 Datasheet HTML 80Page - Renesas Technology Corp SH7261 Datasheet HTML 81Page - Renesas Technology Corp SH7261 Datasheet HTML 82Page - Renesas Technology Corp SH7261 Datasheet HTML 83Page - Renesas Technology Corp Next Button
Zoom Inzoom in Zoom Outzoom out
 79 / 1348 page
background image
Section 2 CPU
Rev. 2.00 Sep. 07, 2007 Page 47 of 1312
REJ09B0320-0200
The table below shows the format of instruction codes, operation, and execution states. They are
described by using this format according to their classification.
Instruction
Instruction Code
Operation
Execution
States
T Bit
Indicated by mnemonic.
Explanation of Symbols
Rm:
Source register
Rn:
Destination register
imm: Immediate data
disp: Displacement*
2
Indicated in MSB
↔
LSB order.
Explanation of Symbols
mmmm: Source register
nnnn: Destination register
0000: R0
0001: R1
.........
1111: R15
iiii:
Immediate data
dddd:
Displacement
Indicates summary of
operation.
Explanation of Symbols
→, ←: Transfer direction
(xx):
Memory operand
M/Q/T: Flag bits in SR
&:
Logical AND of each bit
|:
Logical OR of each bit
^:
Exclusive logical OR of
each bit
~:
Logical NOT of each bit
<<n: n-bit left shift
>>n: n-bit right shift
Value when no
wait states are
inserted.*
1
Value of T bit after
instruction is
executed.
Explanation of
Symbols
—: No change
Notes: 1. Instruction execution cycles: The execution cycles shown in the table are minimums. In
practice, the number of instruction execution states will be increased in cases such as
the following:
a. When there is a conflict between an instruction fetch and a data access
b. When the destination register of a load instruction (memory
→ register) is the same
as the register used by the next instruction.
2. Depending on the operand size, displacement is scaled by
×1, ×2, or ×4. For details,
refer to the SH-2A, SH2A-FPU Software Manual.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


датащи скачать

Go To PDF Page


ссылки URL



Вашему бизинису помогли Аллдатащит?  [ DONATE ] 

Что такое Аллдатащит   |   реклама   |   контакт   |   Конфиденциальность   |   Ссылка на техническое описание    |   обмен ссыками   |   поиск по производителю
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com