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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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SH7261 датащи(PDF) 70 Page - Renesas Technology Corp |
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SH7261 датащи(HTML) 70 Page - Renesas Technology Corp |
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70 / 1348 page  Section 2 CPU Rev. 2.00 Sep. 07, 2007 Page 38 of 1312 REJ09B0320-0200 2.3.3 Instruction Format The instruction formats and the meaning of source and destination operands are described below. The meaning of the operand depends on the instruction code. The symbols used are as follows: • xxxx: Instruction code • mmmm: Source register • nnnn: Destination register • iiii: Immediate data • dddd: Displacement Table 2.9 Instruction Formats Instruction Formats Source Operand Destination Operand Example 0 format xxxx xxxx xxxx xxxx 15 0 — — NOP — nnnn: Register direct MOVT Rn Control register or system register nnnn: Register direct STS MACH,Rn R0 (Register direct) nnnn: Register direct DIVU R0,Rn Control register or system register nnnn: Register indirect with pre- decrement STC.L SR,@-Rn mmmm: Register direct R15 (Register indirect with pre- decrement) MOVMU.L Rm,@-R15 R15 (Register indirect with post- increment) nnnn: Register direct MOVMU.L @R15+,Rn n format xxxx xxxx xxxx nnnn 15 0 R0 (Register direct) nnnn: (Register indirect with post- increment) MOV.L R0,@Rn+ |
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