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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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SH7261 датащи(PDF) 59 Page - Renesas Technology Corp |
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SH7261 датащи(HTML) 59 Page - Renesas Technology Corp |
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59 / 1348 page  Section 2 CPU Rev. 2.00 Sep. 07, 2007 Page 27 of 1312 REJ09B0320-0200 (2) Procedure Register (PR) PR stores the return address of a subroutine call using a BSR, BSRF, or JSR instruction, and is referenced by a subroutine return instruction (RTS). (3) Program Counter (PC) PC indicates the address of the instruction being executed. 2.1.4 Register Banks For the nineteen 32-bit registers comprising general registers R0 to R14, control register GBR, and system registers MACH, MACL, and PR, high-speed register saving and restoration can be carried out using a register bank. The register contents are automatically saved in the bank after the CPU accepts an interrupt that uses a register bank. Restoration from the bank is executed by issuing a RESBANK instruction in an interrupt processing routine. This LSI has 15 banks. For details, see the SH-2A, SH2A-FPU Software Manual and section 6.8, Register Banks. 2.1.5 Initial Values of Registers Table 2.1 lists the values of the registers after a reset. Table 2.1 Initial Values of Registers Classification Register Initial Value R0 to R14 Undefined General registers R15 (SP) Value of the stack pointer in the vector address table SR Bits I[3:0] are 1111 (H'F), BO and CS are 0, reserved bits are 0, and other bits are undefined GBR, TBR Undefined Control registers VBR H'00000000 MACH, MACL, PR Undefined System registers PC Value of the program counter in the vector address table |
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