SH7261 datasheet(97/1348 Pages) RENESAS

номер детали	SH7261

подробное описание детали	32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

PDF	1348 Pages

Scroll/Zoom	100%

производитель	RENESAS [Renesas Technology Corp]

домашняя страница	http://www.renesas.com

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97 / 1348 page

Section 2 CPU

Rev. 2.00 Sep. 07, 2007 Page 65 of 1312

REJ09B0320-0200

(1)

Reset State

In the reset state, the CPU is reset. There are two kinds of reset, power-on reset and manual reset.

(2)

Exception Handling State

The exception handling state is a transient state that occurs when exception handling sources such

as resets or interrupts alter the CPU’s processing state flow.

For a reset, the initial values of the program counter (PC) (execution start address) and stack

pointer (SP) are fetched from the exception handling vector table and stored; the CPU then

branches to the execution start address and execution of the program begins.

For an interrupt, the stack pointer (SP) is accessed and the program counter (PC) and status

from the exception handling vector table; the CPU then branches to that address and the program

starts executing, thereby entering the program execution state.

(3)

Program Execution State

In the program execution state, the CPU sequentially executes the program.

(4)

Power-Down State

In the power-down state, the CPU stops operating to reduce power consumption. The SLEEP

instruction places the CPU in sleep mode, software standby mode, or deep standby mode.

SH7261 датащи(PDF) 97 Page - Renesas Technology Corp