SH7261 datasheet(71/1348 Pages) RENESAS

номер детали	SH7261

подробное описание детали	32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

PDF	1348 Pages

Scroll/Zoom	100%

производитель	RENESAS [Renesas Technology Corp]

домашняя страница	http://www.renesas.com

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71 / 1348 page

Section 2 CPU

Rev. 2.00 Sep. 07, 2007 Page 39 of 1312

REJ09B0320-0200

Instruction Formats

Source

Operand

Destination

Operand

Example

mmmm: Register

direct

Control register or

system register

LDC

Rm,SR

mmmm: Register

indirect with post-

increment

Control register or

system register

LDC.L @Rm+,SR

mmmm: Register

indirect

—

JMP

@Rm

mmmm: Register

indirect with pre-

decrement

R0 (Register direct) MOV.L @-Rm,R0

m format

xxxx

mmmm

xxxx

mmmm: PC relative

using Rm

—

BRAF

mmmm: Register

direct

nnnn: Register

direct

ADD

Rm,Rn

mmmm: Register

direct

nnnn: Register

indirect

MOV.L Rm,@Rn

mmmm: Register

indirect with post-

increment (multiply-

and-accumulate)

nnnn*: Register

indirect with post-

increment (multiply-

and-accumulate)

MACH, MACL

MAC.W

@Rm+,@Rn+

mmmm: Register

indirect with post-

increment

nnnn: Register

direct

MOV.L

@Rm+,Rn

mmmm: Register

direct

nnnn: Register

indirect with pre-

decrement

MOV.L

Rm,@-Rn

nm format

nnnn

xxxx

mmmm

mmmm: Register

direct

nnnn: Indexed

MOV.L

Rm,@(R0,Rn)

md format

xxxx

dddd

mmmm

xxxx

mmmmdddd:

with displacement

R0 (Register direct) MOV.B

@(disp,Rm),R0

nd4 format

xxxx

dddd

nnnn

R0 (Register direct) nnnndddd:

with displacement

MOV.B

R0,@(disp,Rn)

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