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SH7261 датащи(PDF) 35 Page - Renesas Technology Corp

номер детали SH7261
подробное описание детали  32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
PDF  1348 Pages
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производитель  RENESAS [Renesas Technology Corp]
домашняя страница  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7261 датащи(HTML) 35 Page - Renesas Technology Corp

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Section 1 Overview
Rev. 2.00 Sep. 07, 2007 Page 3 of 1312
REJ09B0320-0200
Item
Features
Floating-point Unit
(FPU)
• Floating-point co-processor included
• Supports single-precision (32-bit) and double-precision (64-bit)
• Supports data type and exceptions that conforms to IEEE754 standard
• Two rounding modes: Round to nearest and round to zero
• Denormalization modes: Flush to zero
• Floating-point registers
Sixteen 32-bit floating-point registers (single-precision
× 16 words or
double-precision
× 8 words)
Two 32-bit floating-point system registers
• Supports FMAC (multiplication and accumulation) instructions
• Supports FDIV (division) and FSQRT (square root) instructions
• Supports FLDI0/FLDI1 (load constant 0/1) instructions
• Instruction execution time
Latency (FAMC/FADD/FSUB/FMUL): Three cycles (single-precision),
eight cycles (double-precision)
Pitch (FAMC/FADD/FSUB/FMUL): One cycle (single-precision), six
cycles (double-precision)
Note: FMAC only supports single-precision
• 5-stage pipeline
Cache
• Instruction cache: 8 Kbytes
• Operand cache: 8 Kbytes
• 128-entry, 4-way set associative, 16-byte block length configuration
each for the instruction cache and operand cache
• Write-back, write-through and LRU replacement algorithm
• Cache locking function available (only for operand cache); ways 2 and
3 can be locked



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