ECP2 datasheet(3/386 Pages) LATTICE

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1-2

Introduction

Lattice Semiconductor

LatticeECP2/M Family Data Sheet

Table 1-2. LatticeECP2M (Including “S-Series”) Family Selection Guide

Introduction

The LatticeECP2/M family of FPGA devices is optimized to deliver high performance features such as advanced

DSP blocks, high speed SERDES (LatticeECP2M family only) and high speed source synchronous interfaces in an

economical FPGA fabric. This combination was achieved through advances in device architecture and the use of

90nm technology.

The LatticeECP2/M FPGA fabric is optimized with high performance and low cost in mind. The LatticeECP2/M

devices include LUT-based logic, distributed and embedded memory, Phase Locked Loops (PLLs), Delay Locked

Loops (DLLs), pre-engineered source synchronous I/O support, enhanced sysDSP blocks and advanced conﬁgu-

ration support, including encryption (“S” versions only) and dual boot capabilities.

The LatticeECP2M device family features high speed SERDES with PCS. These high jitter tolerance and low trans-

mission jitter SERDES with PCS blocks can be conﬁgured to support an array of popular data protocols including

PCI Express, Ethernet (1GbE and SGMII), OBSAI and CPRI. Transmit Pre-emphasis and Receive Equalization

settings make SERDES suitable for chip to chip and small form factor backplane applications.

The ispLEVER

® design tool suite from Lattice allows large complex designs to be efﬁciently implemented using the

LatticeECP2/M FPGA family. Synthesis library support for LatticeECP2/M is available for popular logic synthesis

tools. The ispLEVER tool uses the synthesis tool output along with the constraints from its ﬂoor planning tools to

place and route the design in the LatticeECP2/M device. The ispLEVER tool extracts the timing from the routing

and back-annotates it into the design for timing veriﬁcation.

Lattice provides many pre-engineered IP (Intellectual Property) ispLeverCORE™ modules for the LatticeECP2/M

family. By using these IP cores as standardized blocks, designers are free to concentrate on the unique aspects of

their design, increasing their productivity.

Device

ECP2M20

ECP2M35

ECP2M50

ECP2M70

ECP2M100

LUTs (K)

sysMEM Blocks (18kb)

114

225

246

288

Embedded Memory (Kbits)

1217

2101

4147

4534

5308

Distributed Memory (Kbits)

101

145

202

sysDSP Blocks

18x18 Multipliers

168

GPLL+SPLL+DLL

2+6+2

Maximum Available I/O

304

410

436

520

Packages and SERDES / I/O Combinations

256-ball fpBGA (17 x 17 mm)

4 / 140

484-ball fpBGA (23 x 23 mm)

4 / 304

4 / 303

4 / 270

672-ball fpBGA (27 x 27 mm)

4 / 410

8 / 372

900-ball fpBGA (31 x 31 mm)

8 / 410

16 / 416

1152-ball fpBGA (35 x 35 mm)

16 / 436

16 / 520

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