ECP2 datasheet(7/386 Pages) LATTICE

7 / 386 page

2-4

Architecture

Lattice Semiconductor

LatticeECP2/M Family Data Sheet

Figure 2-4. Slice Diagram

Table 2-2. Slice Signal Descriptions

Function

Type

Signal Names

Description

Input

Data signal

A0, B0, C0, D0

Inputs to LUT4

Input

Data signal

A1, B1, C1, D1

Inputs to LUT4

Input

Multi-purpose

Multipurpose Input

Input

Multi-purpose

Multipurpose Input

Input

Control signal

Clock Enable

Input

Control signal

LSR

Local Set/Reset

Input

Control signal

CLK

System Clock

Input

Inter-PFU signal

Fast Carry-in

Input

Inter-slice signal

FXA

Intermediate signal to generate LUT6 and LUT7

Input

Inter-slice signal

FXB

Intermediate signal to generate LUT6 and LUT7

Output

Data signals

F0, F1

LUT4 output register bypass signals

Output

Data signals

Q0, Q1

Output

Data signals

OFX0

Output of a LUT5 MUX

Output

Data signals

OFX1

Output of a LUT6, LUT7, LUT8

2 MUX depending on the slice

Output

Inter-PFU signal

FCO

Slice 2 of each PFU is the fast carry chain output

1. See Figure 2-4 for connection details.

2. Requires two PFUs.

LUT4 &

CARRY*

LUT4 &

CARRY*

SLICE

FF*

OFX0

CLK

LSR

FF*

OFX1

F/SUM

FCI From Different Slice/PFU

FCO To Different Slice/PFU

LUT5

Mux

From

Routing

FXB

FXA

For Slices 0 and 2, memory control signals are generated from Slice 1 as follows:

WCK is CLK

WRE is from LSR

DI[3:2] for Slice 2 and DI[1:0] for Slice 0 data

WAD [A:D] is a 4bit address from slice 1 LUT input

* Not in Slice 3

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