ECP2 datasheet(52/386 Pages) LATTICE

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Architecture

Lattice Semiconductor

LatticeECP2/M Family Data Sheet

for checking soft errors (SED) in SRAM. This SED operation can be run in the background during user mode. If a

soft error occurs, during user mode (normal operation) the device can be programmed to either reload from a

known good boot image or generate an error signal.

For further information about Soft Error Detect (SED) support, please see the list of additional technical documen-

tation at the end of this data sheet.

External Resistor

LatticeECP2/M devices require a single external, 10K ohm ±1% value between the XRES pin and ground. Device

conﬁguration will not be completed if this resistor is missing. There is no boundary scan register on the external

resistor pad.

On-Chip Oscillator

Every LatticeECP2/M device has an internal CMOS oscillator which is used to derive a Master Clock for conﬁgura-

tion. The oscillator and the Master Clock run continuously and are available to user logic after conﬁguration is com-

pleted. The software default value of the Master Clock is 2.5MHz. Table 2-16 lists all the available Master

Conﬁguration Clock frequencies for normal non-encrypted mode and encrypted mode. When a different Master

Clock is selected during the design process, the following sequence takes place:

Device powers up with a Master Clock frequency of 3.1MHz.

During conﬁguration, users select a different master clock frequency.

The Master Clock frequency changes to the selected frequency once the clock conﬁguration bits are received.

If the user does not select a master clock frequency, then the conﬁguration bitstream defaults to the Master

Clock frequency of 2.5MHz.

This internal CMOS oscillator is available to the user by routing it as an input clock to the clock tree. For further

information about the use of this oscillator for conﬁguration or user mode, please see the list of additional technical

documentation at the end of this data sheet.

Table 2-16. Selectable Master Clock (CCLK) Frequencies During Conﬁguration

Density Shifting

The LatticeECP2/M family is designed to ensure that different density devices in the same family and in the same

package have the same pinout. Furthermore, the architecture ensures a high success rate when performing design

migration from lower density devices to higher density devices. In many cases, it is also possible to shift a lower uti-

lization design targeted for a high-density device to a lower density device. However, the exact details of the ﬁnal

resource utilization will impact the likelihood of success in each case. Design migration between LatticeECP2 and

LatticeECP2M families is not possible. For speciﬁc requirements relating to sysCONFIG pins of the ECP2M50,

M70 and M100, see the Logic Signal Connections tables.

Non-Encrypted Mode CCLK (MHz)

Encrypted Mode CCLK (MHz)

2.5

13.0

45.0

2.5

4.3

15.0

55.0

5.4

20.0

60.0

10.0

6.9

26.0

—

34.0

8.1

30.0

—

41.0

9.2

34.0

—

45.0

10.0

41.0

130.0

—

1. Software default frequency.

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