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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ECP2 датащи(PDF) 77 Page - Lattice Semiconductor |
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ECP2 датащи(HTML) 77 Page - Lattice Semiconductor |
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77 / 386 page  3-25 DC and Switching Characteristics Lattice Semiconductor LatticeECP2/M Family Data Sheet tDIBSPI Data Invalid Before Clock (Transmit) ECP2-20 — 280 — 280 — 280 ps ECP2-35 — 280 — 280 — 280 ps ECP2-50 — 280 — 280 — 280 ps ECP2-70 — 280 — 280 — 280 ps ECP2M20 — 230 — 230 — 230 ps ECP2M35 — 230 — 230 — 230 ps ECP2M50 — 230 — 230 — 230 ps ECP2M70 — 230 — 230 — 230 ps ECP2M100 — 230 — 230 — 230 ps XGMII I/O Pin Parameters (312 Mbps) 5 tSUXGMII Data Setup Before Read Clock ECP2/M 480 — 480 — 480 — ps tHXGMII Data Hold After Read Clock ECP2/M 480 — 480 — 480 — ps tDVBCKXGMII Data Valid Before Clock ECP2/M 960 — 960 — 960 — ps tDVACKXGMII Data Valid After Clock ECP2/M 960 — 960 — 960 — ps Primary fMAX_PRI 7 Frequency for Primary Clock Tree ECP2/M — 420 — 357 — 311 MHz tW_PRI Clock Pulse Width for Primary Clock ECP2/M 0.95 — 1.19 — 2.00 — ns tSKEW_PRI Primary Clock Skew Within a Bank ECP2/M — 300 — 360 — 420 ps Edge Clock fMAX_EDGE 7 Frequency for Edge Clock ECP2/M — 420 — 357 — 311 MHz tW_EDGE Clock Pulse Width for Edge Clock ECP2/M 0.95 — 1.19 — 2.00 — ns tSKEW_EDGE Edge Clock Skew Within an Edge of the Device ECP2/M — 300 — 360 — 420 ps 1. General timing numbers based on LVCMOS 2.5, 12mA, 0pf load. 2. DDR timing numbers based on SSTL25 for BGA packages only. 3. DDR2 timing numbers based on SSTL18 for BGA packages only. 4. SPI4.2 and SFI4 timing numbers based on LVDS25 for BGA packages only. 5. XGMII timing numbers based on HSTL class I. A corresponding left/right dedicated clock buffer is used when using the SPI4.2 interface to the left or right edge of the device. For SPI4.2 mode, the software tool will help in selecting the appropriate clock buffer. 6. IP will be used to support DDR and DDR2 memory data rates down to 95MHz. This approach uses a free-running clock and PFU register to sample the data instead of the hardwired DDR memory interface. 7. Using the LVDS I/O standard. 8. ECP2-6 and ECP2-12 do not support SPI4.2 9. The AC numbers do not apply to PCLK6 and PCLK7. 10. Applies to CLKOP only. 11. Please refer to technical note TN1159, LatticeECP2M Pin Assignment Recommendations for best performance. Timing v.A 0.11 LatticeECP2/M External Switching Characteristics 9 (Continued) Over Recommended Operating Conditions Parameter Description Device -7 -6 -5 Units Min. Max. Min. Max. Min. Max. |
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