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ECP2 датащи(PDF) 93 Page - Lattice Semiconductor

номер детали ECP2
подробное описание детали  LatticeECP2/M Family Data Sheet
PDF  386 Pages
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производитель  LATTICE [Lattice Semiconductor]
домашняя страница  http://www.latticesemi.com
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ECP2 датащи(HTML) 93 Page - Lattice Semiconductor

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3-41
DC and Switching Characteristics
Lattice Semiconductor
LatticeECP2/M Family Data Sheet
SERDES External Reference Clock (LatticeECP2M Family Only)
The external reference clock selection and its interface are a critical part of system applications for this product.
Table 3-13 specifies reference clock requirements, over the full range of operating conditions.
Figure 3-13. Jitter Transfer
SERDES Power-Down/Power-Up Specification
Table 3-14. Power-Down and Power-Up Specification
Table 3-13. External Reference Clock Specification (refclkp/refclkn)
Symbol
Description
Min.
Typ.
Max.
Units
FREF
Frequency range
25
—
320
MHz
FREF-PPM
Frequency tolerance
-300
—
300
ppm
VREF-IN-SE
Input swing, single-ended clock
1
100
—
1200
mV, p-p
VREF-IN
Input levels
0
—
VCCP + 0.8
V
VREF-CM-DC
Input common mode range (DC coupled)
0.5
—
1.2
V
VREF-CM-AC
Input common mode range (AC coupled)
2
0
—
1.5
V
DREF
Duty cycle
3
40
—
60
%
TREF-R
Rise time (20% to 80%)
500
1000
ps
TREF-F
Fall time (80% to 20%)
500
1000
ps
ZREF-IN-TERM
Input termination
50/2K
Ohms
CREF-IN-CAP
Input capacitance
4
—
—
1.5
pF
1. The signal swing for a single-ended input clock must be as large as the p-p differential swing of a differential input clock to get the same
gain at the input receiver. Lower swings for the clock may be possible, but will tend to increase jitter.
2. When AC coupled, the input common mode range is determined by:
(Min input level) + (Peak-to-peak input swing)/2 ≤ (Input common mode voltage) ≤ (Max input level) - (Peak-to-peak input swing)/2
3. Measured at 50% amplitude.
4. Input capacitance of 1.5pF is total capacitance, including both device and package.
Symbol
Description
Max.
Units
tPWRDN
Power-down time after all power down register bits set to ‘0’
10
s
tPWRUP
Power-up time after all power down register bits set to ‘1’
5
ms
Frequency (MHz)
Note: This graph is for a nominal device.
-25.00
-20.00
-15.00
-10.00
-5.00
0.00
5.00
0.1
1
10
100
Jitter T.
Gain@25°C,1.20V,
PJ=100ps



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