ECP2 datasheet(23/386 Pages) LATTICE

23 / 386 page

2-20

Architecture

Lattice Semiconductor

LatticeECP2/M Family Data Sheet

Write Through – A copy of the input data appears at the output of the same port during a write cycle. This mode

is supported for all data widths.

Memory Core Reset

The memory array in the EBR utilizes latches at the A and B output ports. These latches can be reset asynchro-

nously or synchronously. RSTA and RSTB are local signals, which reset the output latches associated with Port A

and Port B, respectively. The Global Reset (GSRN) signal resets both ports. The output data latches and associ-

ated resets for both ports are as shown in Figure 2-20.

Figure 2-20. Memory Core Reset

For further information about the sysMEM EBR block, please see the the list of additional technical documentation

at the end of this data sheet.

EBR Asynchronous Reset

EBR asynchronous reset or GSR (if used) can only be applied if all clock enables are low for a clock cycle before the

reset is applied and released a clock cycle after the reset is released, as shown in Figure 2-21. The GSR input to the

EBR is always asynchronous.

Figure 2-21. EBR Asynchronous Reset (Including GSR) Timing Diagram

If all clock enables remain enabled, the EBR asynchronous reset or GSR may only be applied and released after

the EBR read and write clock inputs are in a steady state condition for a minimum of 1/fMAX (EBR clock). The reset

release must adhere to the EBR synchronous reset setup time before the next active read or write clock edge.

SET

LCLR

Output Data

Latches

Memory Core

Port A[17:0]

SET

Port B[17:0]

RSTB

GSRN

Programmable Disable

RSTA

LCLR

Reset

Clock

Enable

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