ECP2 datasheet(46/386 Pages) LATTICE

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2-43

Architecture

Lattice Semiconductor

LatticeECP2/M Family Data Sheet

sets of single-ended input buffers (both ratioed and referenced). One of the referenced input buffers can also

be conﬁgured as a differential input.

The two pads in the pair are described as “true” and “comp”, where the true pad is associated with the positive

side of the differential input buffer and the comp (complementary) pad is associated with the negative side of

the differential input buffer.

Left and Right (Banks 2, 3, 6 and 7) sysI/O Buffer Pairs (50% Differential and 100% Single-Ended Out-

puts)

The sysI/O buffer pairs in the left and right banks of the device consist of two single-ended output drivers, two

sets of single-ended input buffers (both ratioed and referenced) and one differential output driver. One of the ref-

erenced input buffers can also be conﬁgured as a differential input. In these banks the two pads in the pair are

described as “true” and “comp”, where the true pad is associated with the positive side of the differential I/O, and

the comp (complementary) pad is associated with the negative side of the differential I/O.

LVDS differential output drivers are available on 50% of the buffer pairs on the left and right banks.

Bank 8 sysI/O Buffer Pairs (Single-Ended Outputs, Only on Shared Pins When Not Used by Conﬁgura-

tion)

The sysI/O buffers in Bank 8 consist of single-ended output drivers and single-ended input buffers (both ratioed

and referenced). The referenced input buffer can also be conﬁgured as a differential input.

The two pads in the pair are described as “true” and “comp”, where the true pad is associated with the positive

side of the differential input buffer and the comp (complementary) pad is associated with the negative side of the

differential input buffer.

In LatticeECP2 devices, only the I/Os on the bottom banks have programmable PCI clamps. In LatticeECP2M

devices, the I/Os on the left and bottom banks have programmable PCI clamps.

Typical sysI/O I/O Behavior During Power-up

The internal power-on-reset (POR) signal is deactivated when VCC, VCCIO8 and VCCAUX have reached satisfactory

levels. After the POR signal is deactivated, the FPGA core logic becomes active. It is the user’s responsibility to

ensure that all other VCCIO banks are active with valid input logic levels to properly control the output logic states of

all the I/O banks that are critical to the application. For more information about controlling the output logic state with

valid input logic levels during power-up in LatticeECP2/M devices, see the list of additional technical documentation

at the end of this data sheet.

The VCC and VCCAUX supply the power to the FPGA core fabric, whereas the VCCIO supplies power to the I/O buff-

ers. In order to simplify system design while providing consistent and predictable I/O behavior, it is recommended

that the I/O buffers be powered-up prior to the FPGA core fabric. VCCIO supplies should be powered-up before or

together with the VCC and VCCAUX supplies.

Supported sysI/O Standards

The LatticeECP2/M sysI/O buffer supports both single-ended and differential standards. Single-ended standards

can be further subdivided into LVCMOS, LVTTL and other standards. The buffers support the LVTTL, LVCMOS

1.2V, 1.5V, 1.8V, 2.5V and 3.3V standards. In the LVCMOS and LVTTL modes, the buffer has individual conﬁgura-

tion options for drive strength, bus maintenance (weak pull-up, weak pull-down, or a bus-keeper latch) and open

drain. Other single-ended standards supported include SSTL and HSTL. Differential standards supported include

LVDS, MLVDS, BLVDS, LVPECL, RSDS, differential SSTL and differential HSTL. Tables 2-13 and 2-14 show the I/

O standards (together with their supply and reference voltages) supported by LatticeECP2/M devices. For further

information about utilizing the sysI/O buffer to support a variety of standards please see the the list of additional

technical information at the end of this data sheet.

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