ECP2 datasheet(36/386 Pages) LATTICE

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2-33

Architecture

Lattice Semiconductor

LatticeECP2/M Family Data Sheet

Figure 2-30. Input Register Block Top Edge

Output Register Block

The output register block provides the ability to register signals from the core of the device before they are passed

to the sysI/O buffers. The blocks on the PIOs on the left, right and bottom contain a register for SDR operation that

is combined with an additional latch for DDR operation. Figure 2-31 shows the diagram of the Output Register

Block for PIOs on the left, right and the bottom edges. Figure 2-32 shows the diagram of the Output Register Block

for PIOs on the top edge of the device.

In SDR mode, ONEG0 feeds one of the ﬂip-ﬂops that then feeds the output. The ﬂip-ﬂop can be conﬁgured as a D-

type or latch. In DDR mode, ONEG0 and OPOS0 are fed into registers on the positive edge of the clock. Then at

the next clock cycle this registered OPOS0 is latched. A multiplexer running off the same clock selects the correct

By combining the output blocks of the complementary PIOs and sharing some registers from input blocks, a gear-

box function can be implemented, that takes four data streams: ONEG0A, ONEG1A, ONEG1B and ONEG1B.

Figure 2-32 shows the diagram using this gearbox function. For more information about this topic, please see infor-

mation regarding additional documentation at the end of this data sheet.

Fixed Delay

Dynamic Delay

Note: Simplified version does not show CE and SET/RESET details.

*On selected blocks.

(from sysIO

buffer)

CLK0

(from

routing)

DEL[3:0]

INCK*

INDD

D-Type

IPOS0

/LATCH

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