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ECP2 датащи(PDF) 39 Page - Lattice Semiconductor

номер детали ECP2
подробное описание детали  LatticeECP2/M Family Data Sheet
PDF  386 Pages
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производитель  LATTICE [Lattice Semiconductor]
домашняя страница  http://www.latticesemi.com
Logo LATTICE - Lattice Semiconductor

ECP2 датащи(HTML) 39 Page - Lattice Semiconductor

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2-36
Architecture
Lattice Semiconductor
LatticeECP2/M Family Data Sheet
Top Edge
The PICs on the top edge are different from PIOs on the left, right and bottom edges. PIOs on this edge do not
have DDR registers or DQS signals.
The exact DQS pins are shown in a dual function in the Logic Signal Connections table in this data sheet. Addi-
tional detail is provided in the Signal Descriptions table. The DQS signal from the bus is used to strobe the DDR
data from the memory into input register blocks. Interfaces on the left and right edges are designed for DDR mem-
ories that support 16 bits of data, whereas interfaces on the bottom are designed for memories that support 18 bits
of data.
Figure 2-33. DQS Input Routing for the Left and Right Edges of the Device
PIO B
PIO A
PIO B
PIO A
Assigned
DQS Pin
DQS
Delay
sysIO
Buffer
PADA "T"
PADB "C"
LVDS Pair
PADA "T"
PADB "C"
LVDS Pair
PIO A
PIO B
PADA "T"
PADB "C"
LVDS Pair
PIO A
PIO B
PADA "T"
PADB "C"
LVDS Pair
PIO A
PIO B
PADA "T"
PADB "C"
LVDS Pair
PIO A
PIO B
PADA "T"
PADB "C"
LVDS Pair
PIO A
PIO B
PADA "T"
PADB "C"
LVDS Pair
PIO A
PIO B
PADA "T"
PADB "C"
LVDS Pair



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