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ECP2 датащи(PDF) 89 Page - Lattice Semiconductor

номер детали ECP2
подробное описание детали  LatticeECP2/M Family Data Sheet
PDF  386 Pages
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производитель  LATTICE [Lattice Semiconductor]
домашняя страница  http://www.latticesemi.com
Logo LATTICE - Lattice Semiconductor

ECP2 датащи(HTML) 89 Page - Lattice Semiconductor

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DC and Switching Characteristics
Lattice Semiconductor
LatticeECP2/M Family Data Sheet
DLL Timing
Over Recommended Operating Conditions
Parameter
Description
Min.
Typ.
Max.
Units
fREF
Input reference clock frequency (on-chip or off-chip)
100
500
MHz
fFB
Feedback clock frequency (on-chip or off-chip)
100
500
MHz
fCLKOP
1
Output clock frequency, CLKOP
100
500
MHz
fCLKOS
2
Output clock frequency, CLKOS
25
500
MHz
tPJIT
Output clock period jitter (clean input)
250
ps p-p
tCYJIT
Output clock cycle to cycle jitter (clean input)
250
ps p-p
tDUTY
Output clock duty cycle (at 50% levels, 50% duty cycle input clock,
50% duty cycle circuit turned off, time reference delay mode)
35
65
%
tDUTYTRD
Output clock duty cycle (at 50% levels, arbitrary duty cycle input
clock, 50% duty cycle circuit enabled, time reference delay mode)
40
60
%
tDUTYCIR
Output clock duty cycle (at 50% levels, arbitrary duty cycle input
clock, 50% duty cycle circuit enabled, clock injection removal
mode)
40
60
%
tSKEW
3
Output clock to clock skew between two outputs with the same
phase setting
100
ps
tPWH
Input clock minimum pulse width high (at 80% level)
750
ps
tPWL
Input clock minimum pulse width low (at 20% level)
750
ps
tR, tF
Input clock rise and fall time (20% to 80% levels)
1
ns
tINSTB
Input clock period jitter
+/-250
ps
tLOCK
DLL lock time
18,500
cycles
tRSWD
Digital reset minimum pulse width (at 80% level)
3
ns
tPA
Delay step size
16.5
42
59.4
ps
tRANGE1
Max. delay setting for single delay block (144 taps)
2.376
6
8.553
ns
tRANGE4
Max. delay setting for four chained delay blocks
9.504
24
34.214
ns
1. CLKOP runs at the same frequency as the input clock.
2. CLKOS minimum frequency is obtained with divide by 4.
3. This is intended to be a “path-matching” design guideline and is not a measurable specification.
Timing v.A 0.11



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