ECP2 datasheet(49/386 Pages) LATTICE

49 / 386 page

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Architecture

Lattice Semiconductor

LatticeECP2/M Family Data Sheet

SERDES and PCS (Physical Coding Sublayer)

LatticeECP2M devices feature up to 16 channels of embedded SERDES arranged in quads at the corners of the

devices. Figure 2-39 shows the position of the quad blocks in relation to the PFU array for LatticeECP2M70 and

LatticeECP2M100 devices. Table 2-15 shows the location of Quads for all the devices.

Each quad contains four dedicated SERDES (Ch0 to Ch3) for high-speed, full-duplex serial data transfer. Each

quad also has a PCS block that interfaces to the SERDES channels and contains digital logic to support an array of

popular data protocols. PCS also contains logic to the interface to FPGA core.

Figure 2-39. SERDES Quads (LatticeECP2M70/LatticeECP2M100)

Table 2-15. Available SERDES Quads per LatticeECP2M Devices

SERDES Block

A differential receiver receives the serial encoded data stream, equalizes the signal, extracts the buried clock and

de-serializes the data-stream before passing the 8- or 10-bit data to the PCS logic. The transmit channel receives

the parallel (8- or 10-bit) encoded data, serializes the data and transmits the serial bit stream through the differen-

tial buffers. There is a single transmit clock per quad. Figure 2-40 shows a single channel SERDES and its inter-

face to the PCS logic. Each SERDES receiver channel provides a recovered clock to the PCS block and to the

FPGA core logic.

Device

URC Quad

ULC Quad

LRC Quad

LLC Quad

ECP2M20

Available

—

ECP2M35

Available

—

ECP2M50

Available

—

Available

—

ECP2M70

Available

ECP2M100

Available

ULC SERDES Quad

URC SERDES Quad

LRC SERDES Quad

LLC SERDES Quad

Ch 3

PCS Digital Logic

Ch 2

Ch 1

Ch 0

Ch 3

PCS Digital Logic

Ch 2

Ch 1

Ch 0

Ch 3

PCS Digital Logic

Ch 2

Ch 1

Ch 0

Ch 3

PCS Digital Logic

Ch 2

Ch 1

Ch 0

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