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ECP2 датащи(PDF) 14 Page - Lattice Semiconductor |
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ECP2 датащи(HTML) 14 Page - Lattice Semiconductor |
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14 / 386 page ![]() 2-11 Architecture Lattice Semiconductor LatticeECP2/M Family Data Sheet Figure 2-9. Clock Divider Connections Clock Distribution Network LatticeECP2/M devices have eight quadrant-based primary clocks and eight flexible region-based secondary clocks/control signals. Two high performance edge clocks are available on each edge of the device to support high speed interfaces. These clock inputs are selected from external I/Os, the sysCLOCK PLLs, DLLs or routing. These clock inputs are fed throughout the chip via a clock distribution system. Primary Clock Sources LatticeECP2/M devices derive clocks from five primary sources: PLL (GPLL and SPLL) outputs, DLL outputs, CLKDIV outputs, dedicated clock inputs and routing. LatticeECP2/M devices have two to eight sysCLOCK PLLs and two DLLs, located on the left and right sides of the device. There are eight dedicated clock inputs, two on each side of the device, with the exception of the LatticeECP2M 256-fpBGA package devices which have six dedicated clock inputs on the device. Figure 2-10 shows the primary clock sources. RST RELEASE ÷1 ÷2 ÷4 ÷8 CLKO CLKOP (GPLL) CLKOP (DLL) Routing PLL PAD CLKOS (GPLL) CLKOS (DLL) CLKDIV |
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