MPC8313E datasheet(14/92 Pages) FREESCALE

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MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

DDR and DDR2 SDRAM

Table 11 provides the PLL lock times.

DDR and DDR2 SDRAM

This section describes the DC and AC electrical specifications for the DDR SDRAM interface. Note that

DDR SDRAM is GVDD(typ) = 2.5 V and DDR2 SDRAM is GVDD(typ) = 1.8 V.

6.1

DDR and DDR2 SDRAM DC Electrical Characteristics

Table 12 provides the recommended operating conditions for the DDR2 SDRAM component(s) when

GVDD(typ) = 1.8 V.

HRESET/ SRESET assertion (output)

512

—

tPCI_SYNC_IN

HRESET negation to SRESET negation (output)

—

tPCI_SYNC_IN

Input setup time for POR configuration signals (CFG_RESET_SOURCE[0:3] and

CFG_SYS_CLK_IN_DIV ) with respect to negation of PORESET when the device is

in PCI host mode

4—

tSYS_CLK_IN

Input setup time for POR configuration signals (CFG_RESET_SOURCE[0:2] and

CFG_CLKIN_DIV) with respect to negation of PORESET when the device is in PCI

agent mode

4—

tPCI_SYNC_IN

Input hold time for POR configuration signals with respect to negation of HRESET

0—

—

Time for the device to turn off POR configuration signals with respect to the assertion

of HRESET

—4

Time for the device to turn on POR configuration signals with respect to the negation

of HRESET

1—

tPCI_SYNC_IN

1, 3

Notes:

1. tPCI_SYNC_IN is the clock period of the input clock applied to PCI_SYNC_IN. When the device is In PCI host mode the primary

clock is applied to the SYS_CLK_IN input, and PCI_SYNC_IN period depends on the value of CFG_CLKIN_DIV.

2. tSYS_CLK_IN is the clock period of the input clock applied to SYS_CLK_IN. It is only valid when the device is in PCI host mode.

3. POR configuration signals consists of CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV.

Table 11. PLL Lock Times

Parameter/Condition

Min

Max

Unit

Notes

PLL lock times

—

100

μs—

Table 12. DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V

Parameter/Condition

Symbol

Min

Max

Unit

Notes

I/O supply voltage

GVDD

1.7

1.9

I/O reference voltage

MVREF

0.49

× GVDD

0.51

× GVDD

I/O termination voltage

VTT

MVREF –0.04

MVREF + 0.04

Input high voltage

VIH

MVREF +0.125

GVDD +0.3

—

Table 10. RESET Initialization Timing Specifications (continued)

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