MPC8313E datasheet(12/92 Pages) FREESCALE

12 / 92 page

MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

Clock Input Timing

Table 6 shows the estimated core power dissipation of the MPC8313E while transitioning into the

D3warm low power state.

Clock Input Timing

This section provides the clock input DC and AC electrical characteristics for the MPC8313E.

4.1

DC Electrical Characteristics

Table 7 provides the system clock input (SYS_CLK_IN/PCI_SYNC_IN) DC timing specifications for the

MPC8313E.

4.2

AC Electrical Characteristics

The primary clock source for the MPC8313E can be one of two inputs, SYS_CLK_IN or PCI_CLK,

depending on whether the device is configured in PCI host or PCI agent mode. Table 8 provides the system

clock input (SYS_CLK_IN/PCI_CLK) AC timing specifications for the MPC8313E.

Table 6. MPC8313E Low Power Modes Power Dissipation 1,

All interfaces are enabled. For further power savings, disable the clocks to unused

blocks.

333-MHz core, 167-MHz CSB 2

The interfaces are run at the following frequencies: DDR: 167 MHz, eLBC 167 MHz,

PCI 33 MHz, eTSEC1 and 2: 167 MHz, SEC: 167 MHz, USB: 167 MHz. See the SCCR

Maximum 3

Maximum power is based on a voltage of 1.05 V and a junction temperature of 105° C.

Unit

D3 warm

400

Table 7. SYS_CLK_IN DC Electrical Characteristics

Parameter

Condition

Symbol

Min

Max

Unit

Input high voltage

—

VIH

2.7

NVDD +0.3

Input low voltage

—

VIL

–0.3

0.4

SYS_CLK_IN Input current

0 V

≤ VIN ≤ NVDD

IIN

—±10

μA

PCI_SYNC_IN Input current

0 V

≤ VIN ≤ 0.5 V

NVDD – 0.5 V ≤ VIN ≤ NVDD

IIN

—±10

μA

PCI_SYNC_IN Input current

0.5 V

≤ VIN ≤ NVDD – 0.5 V

IIN

—±50

μA

Table 8. SYS_CLK_IN AC Timing Specifications

Parameter/Condition

Symbol

Min

Typical

Max

Unit

Notes

SYS_CLK_IN/PCI_CLK frequency

fSYS_CLK_IN

—

66.67

MHz

SYS_CLK_IN/PCI_CLK cycle time

tSYS_CLK_IN

—

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