MPC8313E datasheet(45/92 Pages) FREESCALE

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MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

12 I2C

This section describes the DC and AC electrical characteristics for the I2C interface.

12.1

I2C DC Electrical Characteristics

Table 46 provides the DC electrical characteristics for the I2C interface.

12.2

I2C AC Electrical Specifications

Table 47 provides the AC timing parameters for the I2C interface.

Table 46. I2C DC Electrical Characteristics

At recommended operating conditions with NVDD of 3.3 V ± 10%.

Parameter

Symbol

Min

Max

Unit Notes

Input high voltage level

VIH

0.7

× NVDD NVDD + 0.3

—

Input low voltage level

VIL

–0.3

0.3

× NVDD V—

Low level output voltage

VOL

00.2

× NVDD V1

Output fall time from VIH(min) to VIL(max) with a bus capacitance from 10

to 400 pF

tI2KLKV 20 + 0.1 × CB

250

Pulse width of spikes which must be suppressed by the input filter

tI2KHKL

050

Capacitance for each I/O pin

—10

—

Input current, (0 V

≤VIN ≤ NVDD)IIN

—± 5

μA4

Notes:

1. Output voltage (open drain or open collector) condition = 3 mA sink current.

2. CB = capacitance of one bus line in pF.

3. Refer to the

MPC8313E PowerQUICC™ II Pro Integrated Host Processor Reference Manual for information on the digital

filter used.

4. I/O pins obstruct the SDA and SCL lines if NVDD is switched off.

Table 47. I2C AC Electrical Specifications

All values refer to VIH (min) and VIL (max) levels (see Table 46).

Parameter

Symbol 1

Min

Max

Unit

SCL clock frequency

fI2C

400

kHz

Low period of the SCL clock

tI2CL

1.3

—

μs

High period of the SCL clock

tI2CH

0.6

—

μs

Setup time for a repeated START condition

tI2SVKH

0.6

—

μs

Hold time (repeated) START condition (after this period, the first clock pulse is generated)

tI2SXKL

0.6

—

μs

Data setup time

tI2DVKH

100

—

Data hold time:

CBUS compatible masters

I2C bus devices

tI2DXKL

—

0 2

—

0.9 3

μs

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