MPC8313E datasheet(86/92 Pages) FREESCALE

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MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

Document Revision History

22 Document Revision History

Table 70 provides a revision history for this hardware specification.

Table 70. Document Revision History

Rev.

Number

Date

Substantive Change(s)

3/2008

• Replaced OVDD with NVDD everywhere

• Added XCOREVDD and XPADVDD to Table 1

• Moved VDD and VDDC to the top of the table before SerDes supplies in Table 2

•In Table 2 split DDR row into two from total current requirement of 425 mA. One for DDR1 (131 mA)

and other for DDR2 (140 mA).

•In Table 2 corrected current requirment numbers for NVDD from 27 mA to 74 mA, LVDD from 60 mA to

16 mA, LVDDA from 85 mA to 22 mA and LVDDB from 85 mA to 44 mA.

•In Table 2 corrected Vdd and Vddc current requirements from 560 mA and 454 mA to 469 and 377

mA, respectively. Corrected Avdd1 and Avdd2 current requirements from 10 mA to 2–3 mA, and

XCOREVDD from 100 mA to 170 mA.

•In Table 2, added row stating junction temperature range of 0 to 105°C. Added footnote 2 stating GPIO

pins may operate from 2.5-V supply as well when configured for different functionality.

•In Section 2.1.2, “Power Supply Voltage Specification,” added a note describing the purpose of

Table 2.

•In Section 3, “Power Characteristics,” added a note describing the purpose of Table 5.

•Rewrote Section 2.2, “Power Sequencing,” and added Figure 2.

•In Table 4, added “but do include core, USB PLL, and a portion of SerDes digital power...” to Note 1.

•In Table 4 corrected “Typical power” to “Maximum power” in note 2 and added a note for Typical Power.

•In Table 4 removed 266-MHz row as 266-MHz core parts are not offered.

•In Table 5, moved Local bus typical power dissipation under LVdd.

• Added Table 6 to show the low power mode power dissipation for D3warm mode.

•In Table 8 corrected SYS_CLK_IN frequency range from 25–66 MHz to 24–66.67 MHz.

• Added Section 8.3, “eTSEC IEEE 1588 AC Specifications”

•In Table 39 changed minimum value of USB input hold tUSIXKH from 0 to 1ns

• Added Table 40 and Table 41 showing USB clock in specifications

•In Table 43, added rows for tLALEHOV, tLALETOT1, tLALETOT2, and tLALETOT3 parameters. Added

Figure 25.

•In Table 47, removed row for rise time (tI2CR). Removed minimum value of tI2CF. Added note 5 stating

that the device does not follow the I2C-BUS Specifications version 2.1 regarding the tI2CF AC

parameter.

•In Table 53, added a note stating: “This specification only applies to GPIO pins that are operating from

a 3.3-V supply. See Table 60 for the power supply listed for the individual GPIO signal.” [

• Added Table 54 to show DC characteristics for GPIO pins supplied by a 2.5-V supply. Same as eTSEC

DC characteristics when operating at 2.5 V.

•In Section 19, “Clocking,” corrected the sentence “When the device is configured as a PCI agent

device, PCI_SYNC_IN is the primary input clock.” to state “When the device is configured as a PCI

agent device, PCI_CLK is the primary input clock.”

• Added “Value is decided by RCWLR[COREPLL]” to note 1 of Figure 42

• Added paragraph and Figure 44 to Section 21.2, “PLL Power Supply Filtering.”

• Added Section 21.4, “SerDes Block Power Supply Decoupling Recommendations

• Removed the two figures on PCI undershoot/overshoot voltages and maximum AC waveforms from

Section 2.1.2, “Power Supply Voltage Specification,”

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