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MPC8313E датащи(PDF) 71 Page - Freescale Semiconductor, Inc

номер детали MPC8313E
подробное описание детали  PowerQUICC??II Pro Processor Hardware Specifications
PDF  92 Pages
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производитель  FREESCALE [Freescale Semiconductor, Inc]
домашняя страница  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8313E датащи(HTML) 71 Page - Freescale Semiconductor, Inc

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MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1
Freescale Semiconductor
71
Clocking
19.1
System PLL Configuration
The system PLL is controlled by the RCWL[SPMF] parameter. Table 63 shows the multiplication factor
encodings for the system PLL.
As described in Section 19, “Clocking,” The LBCM, DDRCM, and SPMF parameters in the reset
configuration word low and the CFG_CLKIN_DIV configuration input signal select the ratio between the
primary clock input (SYS_CLK_IN or PCI_SYNC_IN) and the internal coherent system bus clock
(csb_clk). Table 64 shows the expected frequency values for the CSB frequency for select csb_clk to
SYS_CLK_IN/PCI_SYNC_IN ratios.
Table 63. System PLL Multiplication Factors
RCWL[SPMF]
System PLL Multiplication
Factor
0000
Reserved
0001
Reserved
0010
× 2
0011
× 3
0100
× 4
0101
× 5
0110
× 6
0111–1111
Reserved
Table 64. CSB Frequency Options
CFG_CLKIN_DIV at reset 1
SPMF
csb_clk :Input Clock Ratio 2
Input Clock Frequency (MHz)2
24
25
33.33
66.67
csb_clk Frequency (MHz)
High
0010
2 : 1
133
High
0011
3 : 1
100
High
0100
4 : 1
100
133
High
0101
5 : 1
120
125
167
High
0110
6 : 1
144
150
Low
0010
2 : 1
133
Low
0011
3 : 1
100
Low
0100
4 : 1
100
133



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