MPC8313E datasheet(73/92 Pages) FREESCALE

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MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

Thermal

19.3

Example Clock Frequency Combinations

Table 66 shows several possible frequency combinations that can be selected based on the indicated input

reference frequencies, with RCWLR[LBCM] = 0 and RCWLR[DDRCM] =1, such that the LBC operates

with a frequency equal to the frequency of csb_clk and the DDR controller operates at twice the frequency

of csb_clk.

20 Thermal

This section describes the thermal specifications of the MPC8313E.

0011

03:1

0011

03:1

0011

03:1

For

core_clk:csb_clk ratios of 2.5:1 and 3:1, the core_clk must not exceed its maximum operating frequency of

333 MHz.

Core VCO frequency = Core frequency

× VCO divider. Note that VCO divider has to be set properly so that the

core VCO frequency is in the range of 400–800 MHz.

Table 66. System Clock Frequencies

LBC(lbc_clk)

e300 Core(core_clk)

SYS_

CLK_IN/

PCI_CLK

SPMF 1

System PLL multiplication factor

vcod 2

System PLL VCO divider

vco 3

When considering operating frequencies, the valid core VCO operating range of 400–800 MHz must not be violated.

CSB

(

csb_clk) 4

Due to erratum eTSEC40,

csb_clk frequencies of less than 133 MHz do not support Gigabit Ethernet data rates. The core

frequency must be 333 MHz for Gigabit Ethernet operation. This erratum will be fixed in revision 2 silicon.

DDR

(ddr_clk)

USB

ref 5

Frequency of USB PLL input reference.

× 1

× 1.5 × 2 × 2.5 × 3

25.0

600.0

150.0

300.0

—

37.5

18.8

Note 6

USB reference clock must be supplied from a separate source as it must be 24 or 48 MHz, the USB reference must be

supplied from a separate external source using USB_CLK_IN.

150.0

225

300

375

—

25.0

500.0

125.0

250.0

62.5 31.25 15.6

Note 6

125.0

188

250

313

375

33.3

666.0

166.5

333.0

—

41.63 20.8

Note 6

166.5

250

333

—

33.3

532.8

133.2

266.4

66.6

33.3

16.7

Note 6

133.2

200

266

333

400

48.0

576.0

144.0

288.0

—

18.0

48.0

144.0

216

288

360

—

66.7

533.4

133.3

266.7

66.7 33.34 16.7

Note 6

133.3

200

267

333

400

Table 65. e300 Core PLL Configuration (continued)

RCWL[COREPLL]

core_clk : csb_clk Ratio 1

VCO divider (vcod) 2

0–1

2–5

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