MPC8313E datasheet(87/92 Pages) FREESCALE

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MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

Document Revision History

3/2008

• In Table 60, added LBC_PM_REF_10 & LSRCID3 as muxed with USBDR_PCTL1

•In Table 60, added LSRCID2 as muxed with USBDR_PCTL0

•In Table 60, added LSRCID1 as muxed with USBDR_PWRFAULT

•In Table 60, added LSRCID0 as muxed with USBDR_DRIVE_VBUS

•In Table 60, moved T1, U2,& V2 from VDD to XCOREVDD.

•In Table 60, moved P2, R2, & T3 from VSS to XCOREVSS.

•In Table 60, moved P5, & U4 from VDD to XPADVDD.

•In Table 60, moved P3, & V4 from VSS to XPADVSS.

•In Table 60, removed “Double with pad” for AVDD1 and AVDD2 and moved AVDD1 and AVDD2 to Power

and Ground Supplies section

•In Table 60, added impedance control requirements for SD_IMP_CAL_TX (100 ohms to GND) and

SD_IMP_CAL_RX (200 ohms to GND).

•In Table 60, updated muxing in pinout to show new options for selecting IEEE 1588 functionality.

Added footnote 8

•In Table 60, updated muxing in pinout to show new LBC ECC boot enable control muxed with

eTSEC1_MDC

• Added pin type information for power supplies.

• Removed N1 and N3 from Vss section of Table 60. Added Therm0 and Therm1 (N1 and N3,

respectively). Added note 7 to state: “Internal thermally sensitive resistor, resistor value varies linearly

with temperature. Useful for determining the junction temperature.”

•In Table 62 corrected maximum frequency of Local Bus Frequency from “33–66” to 66 MHz

•In Table 62 corrected maximum frequency of PCI from “24–66” to to 66 MHz

• Added “which is determined by RCWLR[COREPLL],” to the note in Section 19.2, “Core PLL

Configuration” about the vco divider.

• Added “(vcod)” next to VCO divider column in Table 65. Added footnote stating that core_clk

frequency must not exceed its maximum, so 2.5:1 and 3:1

core_clk:csb_clk ratios are invalid for

certain

csb_clk values.

•In Table 66, notes were confusing. Added note 3 for vco column, note 4 for CSB (

csb_clk) column,

note 5 for USB ref column, and note 6 to replace “Note 1”. Clarified note 4 to explain erratum

eTSEC40.

•In Table 66, updated note 6 to specify USB reference clock frequencies limited to 24 and 48 for rev. 2

silicon.

• Replaced Table 68 “Thermal Resistance for TEPBGAII with Heat Sink in Open Flow”.

• Removed last row of Table 19.

• Removed 200 MHz rows from Table 20 and Table 5.

• Changed VIH minimum spec from 2.0 to 2.1 for clock, PIC, JTAG, SPI, and reset pins in Table 9,

Table 44, Table 51, Table 56, and Table 58.

• Added Figure 3 showing the DDR input timing diagram.

•In Table 19, removed “/MDM" from the "MDQS-MDQ/MECC/MDM" text under the

Parameter column for the tCISKEW parameter. MDM is an output signal and should be

removed from the input AC timing spec table (tCISKEW).

• Added “and power” to rows 2 and 3 in Table 10

• Added the sentence “Once both the power supplies...” and PORESET to Section 2.2, “Power

Sequencing,” and Figure 2.

•In Figure 20, corrected “USB0_CLK/USB1_CLK/DR_CLK” with “USBDR_CLK”

•In Table 39, clarified that AC specs are for ULPI only.

6/2007

Initial release.

Table 70. Document Revision History

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