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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MPC8313E датащи(PDF) 29 Page - Freescale Semiconductor, Inc |
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MPC8313E датащи(HTML) 29 Page - Freescale Semiconductor, Inc |
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29 / 92 page  MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 29 Ethernet: Three-Speed Ethernet, MII Management 8.3 eTSEC IEEE 1588 AC Specifications Figure 14 provides the data and command output timing diagram. 1 The output delay is count starting rising edge if t T1588CLKOUT is non-inverting. Otherwise, it is count starting falling edge. Figure 14. eTSEC IEEE 1588 Output AC Timing Figure 15 provides the data and command input timing diagram. Figure 15. eTSEC IEEE 1588 Input AC Timing The IEEE 1588 AC timing specifications are in Table 30. Table 30. eTSEC IEEE 1588 AC Timing Specifications At recommended operating conditions with L/TVDD of 3.3 V ± 5%. Parameter/Condition Symbol Min Typ Max Unit Note TSEC_1588_CLK clock period tT1588CLK 3.8 — TRX_CLK × 9 ns 1, 3 TSEC_1588_CLK duty cycle tT1588CLKH/tT1588CLK 40 50 60 % — TSEC_1588_CLK peak-to-peak jitter tT1588CLKINJ — — 250 ps — Rise time eTSEC_1588_CLK (20%–80%) tT1588CLKINR 1.0 — 2.0 ns — Fall time eTSEC_1588_CLK (80%–20%) tT1588CLKINF 1.0 — 2.0 ns — TSEC_1588_CLK_OUT clock period tT1588CLKOUT 2*tT1588CLK —— ns — TSEC_1588_CLK_OUT TSEC_1588_PULSE_OUT TSEC_1588_TRIG_OUT tT1588OV tT1588CLKOUT tT1588CLKOUTH TSEC_1588_CLK TSEC_1588_TRIG_IN tT1588TRIGH tT1588CLK tT1588CLKH |
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