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TCC76x
Specification Rev. 0.07
February 23, 2005
32-bit RISC Microprocessor for Digital Media Player
TIMER / COUNTER
Preliminary
6-9
23:21
Reserved
0
R/W
20
IRQEN[4]
0
R/W
Enable Interrupt at the rising edge of a counter bit selected by
BITSEL.
19
IRQEN[3]
0
R/W
Enable Interrupt at the end of pre-scale count
18
IRQEN[2]
0
R/W
Enable Interrupt at the end of count
17
IRQEN[1]
0
R/W
Enable Interrupt when the counter value matched with CMP1
16
IRQEN[0]
0
R/W
Enable Interrupt when the counter value matched with CMP0
15:13
Reserved
0
R/W
12:8
IRQRSTAT
0x00
R/W
Interrupt Raw Status. Refer to the description for IRQEN above.
7:5
Reserved
0
R/W
4:0
IRQMSTAT
0x00
R/W
Masked Interrupt Status = IRQRSTAT & IRQEN
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