
TCC76x
Specification Rev. 0.07
February 23, 2005
32-bit RISC Microprocessor for Digital Media Player
ADDRESS & REGISTER MAP
Preliminary
2-10
Table 2.15 CIF Register Map (Base Address = 0x80000B00)
Name
Address
Type
Reset
Description
CPCR
0x00
W
0x00000402
Color/Pattern Configuration Register
656FCR1
0x04
W
0x06FF0000
CCIR656 Configuration Register 1
656FCR2
0x08
W
0x0000010B
CCIR656 Configuration Register 2
IICR1
0x0C
W
0x028001E0
Input Image Configuration Register 1
IICR2
0x10
W
0x00000000
Input Image Configuration Register 2
CDCR1
0x14
W
0x00000003
CIF DMAConfiguration Register
CDCR2
0x18
W
0x20000000
MemoryAddress for Y Channel
CDCR3
0x1C
W
0x28000000
MemoryAddress for Cb(U) Channel
CDCR4
0x20
W
0x2C000000
MemoryAddress for Cr(V) Channel
FIFOSTATE
0x24
R
0x00000000
FIFO Status Register
CIRQ
0x28
W/R
0x00000000
Interrupt & CIF Operating Register
ICCTRL
0x2C
W
0x00000000
Image Clock Control
Table 2.16 DMA Controller Register Map (Base = 0x80000E00)
Name
Address
Type
Reset
Description
ST_SADR0
0x00
R/W
-
Start Address of Source Block
SPARAM0
0x04/0x08
R/W
-
Parameter of Source Block
C_SADR0
0x0C
R
-
CurrentAddress of Source Block
ST_DADR0
0x10
R/W
-
StartAddress of Destination Block
DPARAM0
0x14/0x18
R/W
-
Parameter of Destination Block
C_DADR0
0x1C
R
-
CurrentAddress of Destination Block
HCOUNT0
0x20
R/W
0x00000000
Initial and Current Hop count
C
H
A
N
N
E
L
0
CHCTRL0
0x24
R/W
0x00000000
Channel Control Register
CHCONFIG
0x2C
R/W
-
Channel Configuration Register
ST_SADR1
0x30
R/W
-
Start Address of Source Block
SPARAM1
0x34/0x38
R/W
-
Parameter of Source Block
C_SADR1
0x3C
R
-
CurrentAddress of Source Block
ST_DADR1
0x40
R/W
-
StartAddress of Destination Block
DPARAM1
0x44/0x48
R/W
-
Parameter of Destination Block
C_DADR1
0x4C
R
-
CurrentAddress of Destination Block
HCOUNT1
0x50
R/W
0x00000000
Initial and Current Hop count
C
H
A
N
N
E
L
1
CHCTRL1
0x54
R/W
0x00000000
Channel Control Register