TCC76x
Specification Rev. 0.07
February 23, 2005
32-bit RISC Microprocessor for Digital Media Player
INTRODUCTION
Preliminary
1-20
1.4.4 TCC766 Pin Description
Table 1.6 TCC766 Pin Description
Signal Name
Shared Signal
Ball
Type Description – TCC766
External Memory Interface Pins
SD_CKE
GPIO_B[0]
L9
I/O
SDRAM Clock Enable signal. Active high. / GPIO_B[0]
SD_CLK
GPO
P8
I/O
SDRAM Clock / GPO. SD_CLK can be used as a general
purpose output. Refer to section “MEMORY CONTROLLER”.
(MCFG register Bit[3] and Bit[1])
SD_nCS
SD_nCLK / GPIO_B[1]
M8
I/O
Chip select signal for SDRAM, Active low / Inverted SD_CLK for
DDR SDRAM / GPIO_B[1]
XA[21]
DQM[0]
L7
I/O
External Bus Address Bit [21] / Data I/O Mask 0
XA[20]
DQM[1]
N7
I/O
External Bus Address Bit [20] / Data I/O Mask 1
XA[19]
DQS[1]
L6
I/O
External BusAddress Bit [19] / DDR SDRAM Data Strobe [1]
XA[18]
DQS[0]
L5
I/O
External BusAddress Bit [18] / DDR SDRAM Data Strobe [0]
XA[17]
P7
I/O
External Bus Address Bit [17]
XA[16]
SD_nRAS
D5
I/O
External Bus Address Bit [16] / SDRAM RAS signal
XA[15]
SD_nCAS
N4
I/O
External Bus Address Bit [15] / SDRAM CAS signal
XA[14]
SD_BA[1]
N2
I/O
External Bus Address Bit [14] / SDRAM Bank Address 1
XA[13]
SD_BA[0]
N3
I/O
External Bus Address Bit [13] / SDRAM Bank Address 0.
XA[12]
N5
I/O
External Bus Address Bit [12]
XA[11]
M1
I/O
External Bus Address Bit [11]
XA[10]
M5
I/O
External Bus Address Bit [10]
XA[9]
M3
I/O
External Bus Address Bit [9]
XA[8]
L2
I/O
External Bus Address Bit [8]
XA[7]
L4
I/O
External Bus Address Bit [7]
XA[6]
K3
I/O
External Bus Address Bit [6]
XA[5]
J4
I/O
External Bus Address Bit [5]
XA[4]
P14
I/O
External Bus Address Bit [4]
XA[3]
J2
I/O
External Bus Address Bit [3]
XA[2]
J3
I/O
External Bus Address Bit [2]
XA[1]
J5
I/O
External Bus Address Bit [1]
XA[0]
H4
I/O
External Bus Address Bit [0]
XD[15]
H5
I/O
External Bus Data Bit [15]
XD[14]
L3
I/O
External Bus Data Bit [14]
XD[13]
F2
I/O
External Bus Data Bit [13]
XD[12]
E1
I/O
External Bus Data Bit [12]
XD[11]
E9
I/O
External Bus Data Bit [11]
XD[10]
F3
I/O
External Bus Data Bit [10]
XD[9]
D1
I/O
External Bus Data Bit [9]
XD[8]
A2
I/O
External Bus Data Bit [8]
XD[7]
B1
I/O
External Bus Data Bit [7]
XD[6]
F5
I/O
External Bus Data Bit [6]
XD[5]
C2
I/O
External Bus Data Bit [5]
XD[4]
D3
I/O
External Bus Data Bit [4]
XD[3]
G5
I/O
External Bus Data Bit [3]
XD[2]
F10
I/O
External Bus Data Bit [2]
XD[1]
H16
I/O
External Bus Data Bit [1]
XD[0]
F11
I/O
External Bus Data Bit [0]
nCS[3]
GPIO_B[5]
M9
I/O
External Bus Chip Select 3 / GPIO_B[5]. This pin should
be connected to FCSN.
nCS[2]
GPIO_B[4] / TESTCS2
R7
I/O
External Bus Chip Select 2 / GPIO_B[4]. This pin has an
internal connection to the USB2.0 module. Do not use for
external components.
nCS[1]
GPIO_B[3]
R8
I/O
External Bus Chip Select 1 / GPIO_B[3]
nCS[0]
GPIO_B[2] / TESTCS0
P6
I/O
External Bus Chip Select 0 / GPIO_B[2]. This pin has an
internal connection to the USB2.0 module. Do not use for
external components.
nWE
N8
I/O
Static Memory Write Enable signal. Active low.
nOE
D12
I/O
Static Memory Output Enable signal. Active low.
READY
K13
I
Ready information from external device.
FCSN
C14
I
NOR Flash Chip Select. Should be connected to nCS[3].
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