TCC76x
Specification Rev. 0.07
February 23, 2005
32-bit RISC Microprocessor for Digital Media Player
INTERRUPT CONTROLLER
Preliminary
5-3
Interrupt Enable Register (IEN)
0x80000100
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
CIF
I2C
ADC
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MEN TC32 DMA
LCD CDIF
UBH
GS
UB
UT
TC
I2T
I2R
E3
E2
E1
E0
MEN [15]
Master Enable
0
All interrupts are disabled.
1
Any interrupt enabled by corresponding bit[18:0] can be generated to CPU
*) Master Enable functionality is not effective if RDYIRQEN bit of Miscellaneous
Configuration Register is set as “1”.
Bit Field
Interrupt Request Control
1 = Interrupt enabled, 0 = Interrupt disabled
CIF [18]
Camera Interface interrupt control
I2C [17]
I2C interrupt control
ADC [16]
ADC interrupt control
RDY [15]
External Bus READY interrupt control. This bit is effective only when
RDYIRQEN bit of Miscellaneous Configuration Register is set to high.
TC32 [14]
32-bit Timer interrupt control
DMA [13]
DMA interrupt control
LCD [12]
LCD interrupt control
CDIF [11]
CDIF interrupt control
UBH [10]
USB Host interrupt control
GS [9]
GSIO interrupt control
UB [8]
USB interrupt control
UT [7]
UART/IrDA interrupt control
TC [6]
Timer/Counter interrupt control
I2T [5]
I2S TX interrupt control
I2R [4]
I2S RX interrupt control
E3 [3]
External interrupt request 3 control
E2 [2]
External interrupt request 2 control
E1 [1]
External interrupt request 1 control
E0 [0]
External interrupt request 0 control
Clear Interrupt Request Register (CREQ)
0x80000104
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
CIF
I2C
ADC
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RDY
TC32 DMA
LCD CDIF
UBH
GS
UB
UT
TC
I2T
I2R
E3
E2
E1
E0
By writing “1” to each field, the interrupt request flag of corresponding interrupt is cleared. Writing to “0”
doesn’t mean anything and the corresponding flag remains its previous state.
Interrupt Request Register (IREQ)
0x80000108
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
CIF
I2C
ADC
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RDY
TC32 DMA
LCD CDIF
UBH
GS
UB
UT
TC
I2T
I2R
E3
E2
E1
E0
If each field is “1”, it means that the corresponding interrupt has been requested. If each peripheral has its own
request flags, it means at least one of those flags has been set.
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