TCC76x
Specification Rev. 0.07
February 23, 2005
32-bit RISC Microprocessor for Digital Media Player
INTRODUCTION
Preliminary
1-22
Signal Name
Shared Signal
Ball
Type Description – TCC766
GPIO_A[8] / BW[0]
SDIN
E7
I/O
GPIO_A[8] / Bus Width bit 0. The status of BW[1:0] is latched at the
rising edge of nRESET and used to determine external bus width.
Refer to section “MEMORY CONTROLLER” for BW[1:0]
description.
GPIO_A[7]
SDI1 / FGPIO[7]
B7
I/O
GPIO_A[7] / GSIO1 Data In / Fast GPIO bit 7
GPIO_A[6]
TESTRST
A7
I/O
GPIO_A[6] / Reset for the internal USB2.0 module. Pull-down for
normal operation.
GPIO_A[5]
TESTUSB
F9
I/O
GPIO_A[5] / Mode Selection for the internal USB2.0 module. Pull-
up for normal operation.
GPIO_A[4]
SDO1 / FGPIO[4]
B10
I/O
GPIO_A[4] / GSIO1 Data Output / Fast GPIO bit 4
GPIO_A[3]
SDI0 / CDAI / FGPIO[3]
D9
I/O
GPIO_A[3] / GSIO0 Data In / CD Interface Data / Fast GPIO bit 3.
This pin has an internal pull-up resistor.
GPIO_A[2]
FRM0 / CLRCK / FGPIO[2]
E10
I/O
GPIO_A[2] / GSIO0 FRM / CD Interface LRCK / Fast GPIO bit 2
This pin has an internal pull-up resistor.
GPIO_A[1]
SCK0 / CBCLK / FGPIO[1]
E11
I/O
GPIO_A[1] / GSIO0 Clock / CD Interface BCLK / Fast GPIO bit 1
This pin has an internal pull-up resistor.
GPIO_A[0]
SDO0 / FGPIO[0]
M4
I/O
GPIO_A[0] / GSIO0 Data Out / FGPIO[0]
This pin has an internal pull-up resistor.
GPIO_B[29]
USBH_DN
N10
I/O
GPIO_B[29] / USBH_DN
GPIO_B[28]
USBH_DP
R10
I/O
GPIO_B[28] / USBH_DP
GPIO_B[27]
USB_DN
T8
I/O
GPIO_B[27] / USB_DN
GPIO_B[26]
USB_DP
P9
I/O
GPIO_B[26] / USB_DP
GPIO_B[25]
DAI
M13
I/O
GPIO_B[25] / I2S Interface Data In.
Should be connected
externally toADCDAT pin.
GPIO_B[24] / BM[2]
DAO
M14
I/O
GPIO_B[24] / Boot Mode bit 2 / I2S Interface Data Out.
The status of BM[2:0] is latched at the rising edge of nRESET and
used to determine the system boot mode. Refer to sections
“BOOTING PROCEDURE” and “MEMORY CONTROLLER” for
detailed description on BM[2:0].
Refer to “Functional Block Diagram” for more information
about internal connectivity.
GPIO_B[23]
MCLK
N6
I/O
GPIO_B[23] / I2S Interface Master Clock.
Refer to “Functional Block Diagram” for more information
about internal connectivity.
GPIO_B[22] / BM[1]
LRCK
L14
I/O
GPIO_B[22] / Boot Mode bit 1 / I2S Interface LRCK.
The status of BM[2:0] is latched at the rising edge of nRESET and
used to determine the system boot mode. Refer to sections
“BOOTING PROCEDURE” and “MEMORY CONTROLLER” for
detailed description on BM[2:0].
Internal pull-down resistor is active at power up.
GPIO_B[21] / BM[0]
BCLK
N12
I/O
GPIO_B[21] / Boot Mode bit 0 / I2S Interface BCLK.
The status of BM[2:0] is latched at the rising edge of nRESET and
used to determine the system boot mode. Refer to sections
“BOOTING PROCEDURE” and “MEMORY CONTROLLER” for
detailed description on BM[2:0].
Internal pull-down resistor is active at power up.
GPIO_B[9]
UT_RX
N11
I/O
GPIO_B[9 ] / UART RX Signal
GPIO_B[8]
UT_TX / SD_nCS
M11
I/O
GPIO_B[8] / UARTTX Signal / DDR SDRAM Chip Select
GPIO_B[7]
L10
I/O
GPIO_B[7]
GPIO_B[5]
nCS[3]
M9
I/O
GPIO_B[5] / External Chip Select 3. Should be
connected externally to FCSN.
GPIO_B[4]
nCS[2] / TESTCS2
R7
I/O
GPIO_B[4] / External Chip Select 2. This pin has an
internal connection to the USB2.0 module. Do not connect
to external components.
GPIO_B[3]
nCS[1]
R8
I/O
GPIO_B[3] / External Chip Select 1
GPIO_B[2]
nCS[0] / TESTCS0
P6
I/O
GPIO_B[2] / External Chip Select 0. This pin has an
internal connection to the USB2.0 module. Do not connect
external components.
GPIO_B[1]
SD_nCS / SD_nCLK
M8
I/O
GPIO_B[1] / Chip select for SDRAM / Inverted Clock for DDR
SDRAM.
GPIO_B[0]
SD_CKE
L9
I/O
GPIO_B[0] / SDRAM clock control
GPIO_D[17]
FGPIO[10] / SCL
B16
I/O
GPIO_D[17] / Fast GPIO bit 10 / I2C SCL
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