TCC76 datasheet(43/259 Pages) ETC2

43 / 259 page

TCC76x

Specification Rev. 0.07

February 23, 2005

32-bit RISC Microprocessor for Digital Media Player

INTRODUCTION

Preliminary

1-33

1.4.6 TCC768 Pin Description

Table 1.8 TCC768 Pin Description

Signal Name

Shared Signal

Ball Type Description – TCC768

External Memory Interface Pins

SD_CKE

GPIO_B[0]

I/O

SDRAM Clock Enable signal. Active high. / GPIO_B[0]

SD_CLK

GPO

I/O

SDRAM Clock / GPO. SD_CLK can be used as a general

purpose output. Refer to section “MEMORY CONTROLLER”.

(MCFG register Bit[3] and Bit[1])

SD_nCS

GPIO_B[1]

I/O

Chip select signal for SDRAM,Active low / GPIO_B[1]

XA[21]

DQM[0]

I/O

External Bus Address Bit [21] / Data I/O Mask 0

XA[20]

DQM[1]

I/O

External Bus Address Bit [20] / Data I/O Mask 1

XA[19]

I/O

External BusAddress Bit [19]

XA[18]

I/O

External BusAddress Bit [18]

XA[17]

ND_CLE

I/O

External Bus Address Bit [17] / CLE for NAND Flash

XA[16]

SD_nRAS / ND_ALE

I/O

External Bus Address Bit [16] / SDRAM RAS signal /ALE for

NAND Flash

XA[15]

SD_nCAS

I/O

External Bus Address Bit [15] / SDRAM CAS signal

XA[14]

SD_BA[1]

I/O

External Bus Address Bit [14] / SDRAM Bank Address 1

XA[13]

SD_BA[0]

I/O

External Bus Address Bit [13] / SDRAM Bank Address 0.

XA[12]

I/O

External Bus Address Bit [12]

XA[11]

I/O

External Bus Address Bit [11]

XA[10]

I/O

External Bus Address Bit [10]

XA[9]

I/O

External Bus Address Bit [9]

XA[8]

I/O

External Bus Address Bit [8]

XA[7]

I/O

External Bus Address Bit [7]

XA[6]

I/O

External Bus Address Bit [6]

XA[5]

I/O

External Bus Address Bit [5]

XA[4]

I/O

External Bus Address Bit [4]

XA[3]

I/O

External Bus Address Bit [3]

XA[2]

I/O

External Bus Address Bit [2]

XA[1]

I/O

External Bus Address Bit [1]

XA[0]

I/O

External Bus Address Bit [0]

XD[15]

I/O

External Bus Data Bit [15]

XD[14]

I/O

External Bus Data Bit [14]

XD[13]

I/O

External Bus Data Bit [13]

XD[12]

I/O

External Bus Data Bit [12]

XD[11]

I/O

External Bus Data Bit [11]

XD[10]

I/O

External Bus Data Bit [10]

XD[9]

I/O

External Bus Data Bit [9]

XD[8]

I/O

External Bus Data Bit [8]

XD[7]

I/O

External Bus Data Bit [7]

XD[6]

I/O

External Bus Data Bit [6]

XD[5]

I/O

External Bus Data Bit [5]

XD[4]

I/O

External Bus Data Bit [4]

XD[3]

I/O

External Bus Data Bit [3]

XD[2]

I/O

External Bus Data Bit [2]

XD[1]

A10

I/O

External Bus Data Bit [1]

XD[0]

I/O

External Bus Data Bit [0]

NCS[3]

ND_nOE[3] / GPIO_B[5]

I/O

External Bus Chip Select [3] / NAND Flash Output Enable [3] /

GPIO_B[5]. This pin should be connected to FCSN.

NCS[2]

ND_nOE[2] / GPIO_B[4]

I/O

External Bus Chip Select [2] / NAND Flash Output Enable [2] /

GPIO_B[4]

NCS[1]

ND_nOE[1] / GPIO_B[3]

I/O

External Bus Chip Select [1] / NAND Flash Output Enable [1] /

GPIO_B[3]

NCS[0]

ND_nOE[0] / GPIO_B[2]

I/O

External Bus Chip Select [0] / NAND Flash Output Enable [1] /

GPIO_B[2]

ND_nWE

GPIO_B[7]

L10

I/O

NAND flash WE.Active low. / GPIO_B[7]

nWE

I/O

Static Memory Write Enable signal. Active low.

nOE

I/O

Static Memory Output Enable signal. Active low.

READY

J11

Ready information from external device.

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