
TCC76x
Specification Rev. 0.07
February 23, 2005
32-bit RISC Microprocessor for Digital Media Player
ADDRESS & REGISTER MAP
Preliminary
2-5
Table 2.6 GPIO Register Map (Base = 0x80000300)
Name
Address
Type
Reset
Description
GDATA_A
0x00
R/W
0xFFFFFFFF
GPIO_A Data Register
GIOCON_A
0x04
R/W
0x00000000
GPIO_A Direction Control Register
GSEL_A
0x08
R/W
0x00000000
GPIO_A Function Select Register 1
GTSEL_A
0x0C
R/W
0x00000000
GPIO_A Function Select Register 2
GDATA_B
0x10
R/W
0x3FFFFFFF
GPIO_B Data Register
GIOCON_B
0x14
R/W
0x000000FF
GPIO_B Direction Control Register
GSEL_B
0x18
R/W
0x3C0000FF
GPIO_B Function Select Register 1
GTSEL_B
0x1C
R/W
0x00000000
GPIO_B Function Select Register 2
GDATA_C
0x20
R/W
0xFFFF
GPIO_C Data Register
GIOCON_C
0x24
R/W
0x0000
GPIO_C Direction Control Register
GDATA_D
0x30
R/W
0x7FFF
GPIO_D Data Register
GIOCON_D
0x34
R/W
0x0000
GPIO_D Direction Control Register
Shaded registers are only valid in TCC761.
Table 2.7 Clock Generator Register Map (Base = 0x80000400)
Name
Address
Type
Reset
Description
CKCTRL
0x00
R/W
0x00007FFE
Clock Control Register
PLLMODE
0x04
R/W
0x00002E02
PLL Control Register
SCLKmode
0x08
R/W
0x00082000
System Clock Control Register
DCLKmode
0x0C
R/W
0x00000800
DCLK (DAI/CODEC) Control Register
EACLKmode
0x10
R/W
0x00000000
ADCLK and EX2CLK Control Register
EX1CLKmode
0x14
R/W
0x00000000
EX1CLK Control Register
UTCLKmode
0x18
R/W
0x000001BE
UTCLK (UART) Control Register
UBCLKmode
0x1C
R/W
0x00000000
UBCLK (USB) Control Register
LCLKmode
0x20
R/W
0x00000000
LCLK (LCD) Control Register
TCLKmode
0x24
R/W
0x00000000
TCLK (Timer) Control Register
GCLKmode
0x28
R/W
0x00000000
GCLK (GSIO) Control Register
CIFCLKmode
0x2C
R/W
0x00000000
CIFCLK Control Register
SW_nRST
0x3C
R/W
0x0000FEFF
Software Reset for each peripherals
PWDCTL
0x40
R/W
0x00000000
Power Down Control
DIVMODE
0x44
R/W
0x00000000
Divider Mode Enable (DCO Disable)
HCLKSTOP
0x48
R/W
0x00000000
HCLK Stop Control