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TCC76x
Specification Rev. 0.07
February 23, 2005
32-bit RISC Microprocessor for Digital Media Player
INTERRUPT CONTROLLER
Preliminary
5-5
Masked Interrupt Request Register (MREQ)
0x80000114
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
CIF
I2C
ADC
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RDY
TC32 DMA
LCD CDIF
UBH
GS
UB
UT
TC
I2T
I2R
E3
E2
E1
E0
Same meaning as IREQ except that it represents only that of the enabled interrupts. Only the flags of enabled
interrupts can be checked by this register. It is recommended that use MREQ register instead of IREQ in the
interrupt handler routine.
Test Mode Register (TSTREQ)
0x80000118
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
CIF
I2C
ADC
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RDY
TC32 DMA
LCD CDIF
UBH
GS
UB
UT
TC
I2T
I2R
Reserved
This register can be used to generate an interrupt by writing 1 at the corresponding bit of the internal interrupt
source. This register is for testing purpose only. It must be remained zero during normal operation.
IRQ Raw Status Register (IRQ)
0x80000120
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
CIF
I2C
ADC
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RDY
TC32 DMA
LCD CDIF
UBH
GS
UB
UT
TC
I2T
I2R
E3
E2
E1
E0
This register reflects IREQ bits selected when the corresponding IRQSEL bit is low (IREQ & IRQSEL)
FIQ Raw Status Register (FIQ)
0x80000124
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
CIF
I2C
ADC
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RDY
TC32 DMA
LCD CDIF
UBH
GS
UB
UT
TC
I2T
I2R
E3
E2
E1
E0
This register reflects IREQ bits selected when corresponding IRQSEL bit is high (~IREQ & IRQSEL).
Masked IRQ Raw Status Register (MIRQ)
0x80000128
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
CIF
I2C
ADC
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RDY
TC32 DMA
LCD CDIF
UBH
GS
UB
UT
TC
I2T
I2R
E3
E2
E1
E0
MIRQ = IRQ & IEN
Masked FIQ Raw Status Register (MFIQ)
0x8000012C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
CIF
I2C
ADC
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RDY
TC32 DMA
LCD CDIF
UBH
GS
UB
UT
TC
I2T
I2R
E3
E2
E1
E0
MFIQ = FIQ & IEN
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