TCC76x
Specification Rev. 0.07
February 23, 2005
32-bit RISC Microprocessor for Digital Media Player
DAI & CDIF
Preliminary
4-5
BM [10]
DAI Bit Clock Master Select
0
Set that DAI bit clock is come from external pin
1
Set that DAI bit clock is generated by dividing DAI system clock
FM [9]
DAI Frame Clock Master Select
0
Set that DAI frame clock is come from external pin
1
Set that DAI frame clock is generated by dividing DAI bit clock
CC [8]
CDIF Clock Select
0
Disable CDIF Clock master mode
1
Enable CDIF Clock master mode
BD [7:6]
DAI Bit Clock Divider select
00
Select Div 4 ( 256fs->64fs )
01
Select Div 6 ( 384fs->64fs )
10
Select Div 8 ( 512fs->64fs, 384fs->48fs , 256fs->32fs)
11
Select Div16 ( 512fs->32fs )
FD [5:4]
DAI Frame Clock Divider select
00
Select Div 32 ( 32fs->fs )
01
Select Div 48 ( 48fs->fs )
10
Select Div 64 ( 64fs->fs )
The combination of BD & FD determines that the ratio between main system clock and
the sampling frequency. The multiplication between the division factor of BD and FD
must be equal to this ratio.
BP [3]
DAI Bit Clock Polarity
0
Set that data is captured at positive edge of bit clock
1
Set that data is captured at negative edge of bit clock
CM [2]
CDIF Monitor Mode
0
Disable CDIF monitor mode
1
Enable CDIF monitor mode. Data bypass from CDIF
MM [1]
DAI Monitor Mode
0
Disable DAI monitor mode
1
Enable DAI monitor mode. Transmitter should be enabled. (TE = 1)
LB [0]
DAI Loop-back Mode
0
Disable DAI Loop back mode
1
Enable DAI Loop back mode
Digital Audio Volume Control Register (DAVC)
0x80000044
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
VC<3:0>
The volume of audio output can be manipulated by this register. It has –6dB unit so the output
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