TCC76x
Specification Rev. 0.07
February 23, 2005
32-bit RISC Microprocessor for Digital Media Player
DAI & CDIF
Preliminary
4-4
4.2 Register Description - DAI
Table 4.1 DAI Register Map (Base Address = 0x80000000)
Name
Address Type
Reset
Description
DADI_L0
0x00
R
-
DigitalAudio Left Input Register 0
DADI_R0
0x04
R
-
DigitalAudio Right Input Register 0
DADI_L1
0x08
R
-
DigitalAudio Left Input Register 1
DADI_R1
0x0C
R
-
DigitalAudio Right Input Register 1
DADI_L2
0x10
R
-
DigitalAudio Right Input Register 2
DADI_R2
0x14
R
-
DigitalAudio Right Input Register 2
DADI_L3
0x18
R
-
DigitalAudio Right Input Register 3
DADI_R3
0x1C
R
-
DigitalAudio Right Input Register 3
DADO_L0
0x20
R/W
-
DigitalAudio Left Output Register 0
DADO_R0
0x24
R/W
-
DigitalAudio Right Output Register 0
DADO_L1
0x28
R/W
-
DigitalAudio Left Output Register 1
DADO_R1
0x2C
R/W
-
DigitalAudio Right Output Register 1
DADO_L2
0x30
R/W
-
DigitalAudio Left Output Register 2
DADO_R2
0x34
R/W
-
DigitalAudio Right Output Register 2
DADO_L3
0x38
R/W
-
DigitalAudio Left Output Register 3
DADO_R3
0x3C
R/W
-
DigitalAudio Right Output Register 3
DAMR
0x40
R/W
0x0000
DigitalAudio Mode Register
DAVC
0x44
R/W
0x0000
DigitalAudio Volume Control Register
Digital Audio Mode Register (DAMR)
0x80000040
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
EN
TE
RE
MD
SM
BM
FM
CC
BD<1:0>
FD<1:0>
BP
CM MM
LB
EN [15]
DAI Master Enable
0
Disable DAI module
1
Enable DAI module
TE [14]
DAI Transmitter Enable
0
Disable DAI transmitter
1
Enable DAI transmitter
RE [13]
DAI Receiver Enable
0
Disable DAI receiver
1
Enable DAI receiver
MD [12]
DAI Bus Mode
0
Set DAI bus as IIS bus mode
1
Set DAI bus as MSB justified mode
SM [11]
DAI System Clock Master Select
0
Set that DAI system clock is come from external pin
1
Set that DAI system clock is generated by the clock generator block
The DAI system clock in clock generator is known as DCLK. It’s frequency can be
determined by setting DCLKmode register.
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