TCC76x
Specification Rev. 0.07
February 23, 2005
32-bit RISC Microprocessor for Digital Media Player
INTRODUCTION
Preliminary
1-35
Signal Name
Shared Signal
Ball Type Description – TCC768
GPIO_B[26]
USB_DP
L7
I/O
GPIO_B[26] / USB_DP
GPIO_B[25]
DAI
K10
I/O
GPIO_B[25] / I2S Interface Data In. Should be connected externally to
ADCDAT pin.
GPIO_B[24] / BM[2]
DAO
K11
I/O
GPIO_B[24] / Boot Mode bit 2 / I2S Interface Data Out.
The status of BM[2:0] is latched at the rising edge of nRESET and used
to determine the system boot mode.
GPIO_B[23]
MCLK
K12
I/O
GPIO_B[23] / I2S Interface Master Clock.
GPIO_B[22] / BM[1]
LRCK
L11
I/O
GPIO_B[22] / Boot Mode bit 1 / I2S Interface LRCK.
The status of BM[2:0] is latched at the rising edge of nRESET and used
to determine the system boot mode.
Internal pull-down resistor is active at power up.
GPIO_B[21] / BM[0]
BCLK
J9
I/O
GPIO_B[21] / Boot Mode bit 0 / I2S Interface BCLK.
The status of BM[2:0] is latched at the rising edge of nRESET and used
to determine the system boot mode.
Internal pull-down resistor is active at power up.
GPIO_B[9]
UT_RX
L9
I/O
GPIO_B[9 ] / UART RX Signal
GPIO_B[8]
UT_TX
M10
I/O
GPIO_B[8] / UARTTX Signal
GPIO_B[7]
ND_nWE
L10
I/O
GPIO_B[7] / Write Enable for NAND Flash
GPIO_B[5]
nCS[3]
H6
I/O
GPIO_B[5] / External Chip Select 3
GPIO_B[4]
nCS[2]
J6
I/O
GPIO_B[4] / External Chip Select 2
GPIO_B[3]
nCS[1]
K6
I/O
GPIO_B[3] / External Chip Select 1
GPIO_B[2]
nCS[0]
J5
I/O
GPIO_B[2] / External Chip Select 0
GPIO_B[1]
SD_nCS
L6
I/O
GPIO_B[1] / Chip select for SDRAM
GPIO_B[0]
SD_CKE
J8
I/O
GPIO_B[0] / SDRAM clock control
GPIO_D[17]
FGPIO[10] / SCL
G2
I/O
GPIO_D[17] / Fast GPIO bit 10 / I2C SCL
GPIO_D[16]
FGPIO[9] / SDA
A9
I/O
GPIO_D[16] / Fast GPIO bit 9 / I2C SDA
GPIO_D[15]
FGPIO[8]
G1
I/O
GPIO_D[15] / Fast GPIO bit 8
ADC Input Pins
ADIN_0
G10
AI
General purpose multi-channelADC input 0
ADIN_2
F10
AI
General purpose multi-channelADC input 2
ADIN_4
E10
AI
General purpose multi-channelADC input 4
Clock Pins
XIN
H8
I
Main Crystal Oscillator Input for PLL. 12MHz Crystal must
be used if USB Boot Mode is required. Input voltage must
not exceed VDD_OSC (1.95V max).
XOUT
G9
O
Main Crystal Oscillator Output for PLL
XFILT
G12
AO
PLL filter output. 350pF(
±10%) capacitor is required.
XTIN
K9
I
Sub Crystal Oscillator Input. 32.768kHz is recommended.
Input voltage must not exceed VDD_OSC (1.95V max).
XTOUT
J10
O
Sub Crystal Oscillator Output
JTAG Interface Pins
TDI
C11
I
JTAG serial data input. External pull-up resistor is required.
TMS
D11
I
JTAG test mode select. External pull-up resistor is required.
TCK
C10
I
JTAG test clock. External pull-up resistor is required.
TDO
D10
I/O
JTAG serial data output. External pull-up resistor is required.
nTRST
B10
I
JTAG reset signal. Active low.
Mode Control Pins
MODE1
B11
I
Mode Setting Input 1. Pull-down for normal operation.
PKG1
J7
I
Package ID1. Pull-up for normal operation.
nRESET
J12
I
System Reset. Active low.
Power Pins
VDDIO
F5
PWR
Digital Power for I/O (3.3V)
VDDIO
L1
PWR
Digital Power for I/O (3.3V)
VDDIO
H9
PWR
Digital Power for I/O (3.3V)
VDDIO
D7
PWR
Digital Power for I/O (3.3V)
VDDIO
A8
PWR
Digital Power for I/O (3.3V)
VDDIO
D2
PWR
Digital Power for I/O (3.3V)
VDDIO
A6
PWR
Digital Power for I/O (3.3V)
VDDIO_USB
M12
PWR
Power for USB I/O (3.3V)
VDD_OSC
M11
PWR
Digital Power for Oscillators (1.8V)
Russian ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
