TCC76x
Specification Rev. 0.07
February 23, 2005
32-bit RISC Microprocessor for Digital Media Player
INTRODUCTION
Preliminary
1-12
Signal Name
Shared Signal
Pin # Type Description – TCC761
CLRCK
GPIO_B[15]
86
I/O
CD Data Word Clock Input / GPIO_B[15]
CDAI
GPIO_B[16]
87
I/O
CD Data input / GPIO_B[16]
External Interrupt Pins
EXINT[3]
GPIO_A[15]
204
I/O
External Interrupt Request [3] / GPIO_A[15]
EXINT[2:0]
GPIO_A[14:12]/FGPIO[14:12]
203:201
I/O
External Interrupt Request [2:0] / GPIO_A[14:12] / FGPIO[14:12]
LCD, NTSC/PAL Interface Pins
HSYNC
GPIO_B[17]
165
I/O
Line sync / GPIO_B[17]
VSYNC
GPIO_B[18]
166
I/O
Frame sync / GPIO_B[18]
PXCLK
GPIO_B[19]
167
I/O
Pixel clock / GPIO_B[19]
AC_BIAS
GPIO_B[20]
168
I/O
AC bias control signal / GPIO_B[20]
PD[15:12]
PD[11:6]
PD[5:4]
PD[3:0]
GPIO_A[31:28]
GPIO_A[27:22]
GPIO_A[21:20]
GPIO_A[19:16]
177:174
130:125
122:121
115:112
I/O
Pixel data bus [15:0] / GPIO_A[31:16]
Camera Interface Pins
CISHS
GPIO_D[17]
152
I/O
Horizontal Sync. Input / GPIO_D[17]
CISVS
GPIO_D[16]
151
I/O
Vertical Sync. Input / GPIO_D[16]
CISCLK
GPIO_D[15]
150
I/O
Clock Input / GPIO_D[15]
CISD[7:4]
CISD[3:0]
GPIO_D[21:18]
GPIO_A[3:0]
156:153
172:169
I/O
Data Input[7:0] / GPIO_D[21:18], GPIO_A[3:0]
General Purpose I/O Pins
GPIO_A[31:28]
GPIO_A[27:22]
GPIO_A[21:20]
GPIO_A[19:16]
PD[15:12]
PD[11:6]
PD[5:4]
PD[3:0]
177:174,
130:125
122:121
115:112
I/O
GPIO_A[31:16] / Pixel Data Bus [15:0]
GPIO_A[15]
EXINT[3]
204
I/O
GPIO_A[15] / External Interrupt Request 3
GPIO_A[14:12]
EXINT[2:0] / FGPIO[14:12]
203:201
I/O
GPIO_A[15:12] / External Interrupt Request 3 ~ 0 /
Fast GPIO bits 14 ~ 12
GPIO_A[11]
GPIO_A[10]
GPIO_A[9] / BW[1]
GPIO_A[8] / BW[0]
SDI2 / FGPIO[11] / SCL
FRM2 / FGPIO[10] / SDA
SCK2 / FGPIO[9] / SCL
SDO2 / FGPIO[8] / SDA
192:189
I/O
GPIO_A[11:8] / Bus Width bits 1 ~ 0 / General Purpose Serial I/O 2
Fast GPIO bits 11 ~ 8 / I2C signals.
The status of BW[1:0] is latched at the rising edge of nRESET and
used to determine external bus width. Refer to section “MEMORY
CONTROLLER” for BW[1:0] description.
GPIO_A[7:4]
SDI1 / FGPIO[7]
FRM1 / FGPIO[6]
SCK1 / FGPIO[5]
SDO1 / FGPIO[4]
186:185
182
178
I/O
GPIO_A[7:4] / General Purpose Serial I/O 1 / Fast GPIO bits 7 ~ 4
GPIO_A[3:0]
SDI0 / FGPIO[3] / CISD[3]
FRM0 / FGPIO[2] / CISD[2]
SCK0 / FGPIO[1] / CISD[1]
SDO0 / FGPIO[0] / CISD[0]
172:169
I/O
GPIO_A[3:0] / General purpose serial I/O 0 / Fast GPIO bits 3 ~ 0 /
Camera Interface Data Inputs 3 ~ 0
GPIO_B[29:28]
USBH_DN, USBH_DP
91:90
I/O
GPIO_B[29:28] / USBH_DN, USBH_DP
GPIO_B[27:26]
USB_DN, USB_DP
89:88
I/O
GPIO_B[27:26] / USB_DN, USB_DP
GPIO_B[25]
GPIO_B[24] / BM[2]
GPIO_B[23]
GPIO_B[22] / BM[1]
GPIO_B[21] / BM[0]
DAI
DAO
MCLK
LRCK
BCLK
109
108
107
102
101
I/O
GPIO_B[25:21] / Boot Mode bits 2 ~ 0 / I2S Interface Signals.
The status of BM[2:0] is latched at the rising edge of nRESET and
used to determine the system boot mode. Refer to sections
“BOOTING PROCEDURE” and “MEMORY CONTROLLER” for
detailed description on BM[2:0].
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